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Details, datasheet, quote on part number:MT90826
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| Part: | MT90826 |
| Category: | Logic => Switches |
| Description: | 4096 X 4096 Channel Multiple Rate (2, 4, 8, 16 Mbps) 3.3 V Non-blocking Quad Digital Switch (QDX) With Rate Conversion |
| Company: | Zarlink Semiconductor |
| Datasheet: | Download MT90826 datasheet File size : 802 kB |
| Request For quote: | Find where to buy MT90826
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Datasheet text preview:
MT90826 Quad Digital Switch
Data Sheet Fea tur es
· · · · · · · · · · · · · 4,096 × 4,096 channel non-blocking switching at 8.192 or 16.384Mbps Per-channel variable or constant throughput delay Accepts 32 ST-BUS streams of 2.048Mbps, 4.096Mbps, 8.192Mbps or 16.384Mbps Split Rate mode provides a rate conversion option to convert data from one rate to another rate Automatic frame offset delay measurement for ST-BUS input streams Per-stream input delay programming Per-stream output advancement programming Per-channel high impedance output control Bit Error Monitoring on selected ST-BUS input and output channels. Per-channel message mode Connection memory block programming IEEE-1149.1 (JTAG) Test Port 3.3V local I/O with 5V tolerant inputs and TTL compatible outputs Or dering Information MT90826AL M T 90 8 2 6 A G M T 9 0 8 2 6 AV -40°C · · WAN access system Wireless base stations 1 6 0 Pin MQFP 160 Ball PBGA 1 4 4 Ball LBGA to +85°C
May 2003
De scr ipt ion
The MT90826 Quad Digital Switch has a non-blocking switch capacity of 4,096 x 4,096 channels at a serial bit rate of 8.192Mbps or 16.384Mbps, 2,048 x 2,048 channels at 4.096Mbps and 1024 x 1024 channels at 2.048Mbps. The device has many features that are programmable on a per stream or per channel basis, including message mode, input offset delay and high impedance output control. The per stream input and output delay control is particularly useful for managing large multi-chip switches with a distributed backplane. Operating in Split Rate mode allows rate conversion for switching between two groups of bit rate streams.
App lic at ions
· · · · Medium switching platforms CTI application Voice/data multiplexer Digital cross connects
VDD VSS TMS TDI TD O
TCK
TRST
RESET
ODE
Test Port
STi0/FEi0 STi1/FEi1 · · · STi31/FEi31
Serial to Parallel Converter Internal Registers Connection Memory Multiple Buffer Data Memory Output MU X
Parallel to Serial Converter
STo0 STo1 · · · STo31
Timing Unit
Microprocessor Interface
PLLVDD PLLVSS CLK F0i
DS
CS
R/W
A13-A0
DTA
D15-D0
Figure 1 - Functional Block Diagram
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MT90826
Data Sheet
NC STo22 STo23 VSS VDD STi24/FEi24 STi25/FEi25 STI26/FEi26 STi27/FEi27 VSS STo24 STo25 STo26 STo27 VSS VDD STi28/FEi28 STi29/FEi29 STi30/FEi30 STi31/FEi31 VSS STo28 STo29 STo30 STo31 VSS VDD D0 D1 D2 D3 D4 D5 D6 D7 VSS VDD D8 NC NC
12 1 12 3 12 5 12 7 12 9 13 1 13 3 13 5 13 7 13 9 14 1 14 3 14 5 14 7 14 9 15 1 153 155 157 159 79 77 75 73 71 69 67 65 63
NC STo21 STo20 VSS STi23/FEi23 STi22/FEi22 STi21/FEi21 STi20/FEi20 VDD VSS STo19 STo18 STo17 STo16 VSS STi19/FEi19 STi18/FEi18 STi17/FEi17 STi16/FEi16 VDD VSS STo15 STo14 STo13 STo12 VSS STi15/FEi15 STi14/FEi14 STi13/FEi13 STi12/FEi12 VDD VSS STo11 STo10 STo9 STo8 VSS STi11/FEi11 STi10/FEi10 NC 119 117 115 113 111 109 1 07 105 103 1 01 99 97 95 93 91 89 87 85 83 81 NC STi9/FEi9 STi8/FEi8 VDD VSS STo 7 STo 6 STo 5 STo 4 VSS STi7/FEi7 STi6/FEi6 STi5/FEi5 STi4/FEi4 VDD VSS STo 3 STo 2 STo 1 STo 0 VSS STi3/FEi3 STi2/FEi2 STi1/FEi1 STi0/FEi0 ODE VDD VSS C LK PL LVDD PLLGND NC NC F0 i IC3 VSS IC2 RESET IC1 NC
160 Pin MQFP 28mm x 28mm Pin Pitch 0.65mm
61 59 57 55 53 51 49 47 45 43 41
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NC NC D9 D 10 D 11 D 12 D 13 D 14 D 15 DTA VSS VDD CS R/W DS A0 A1 A2 A3 A4 VSS VDD A5 A6 A7 A8 A9 A1 0 A1 1 A1 2 A1 3 VSS VDD TM S TDI TDO TCK TRST NC NC
Figure 2 - 160-Pin MQFP Pin Connections
Zarlink Semiconductor Inc.
Data Sheet
MT90826
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A STi26 B S T i 27 C S T o 26 S T o 2 5 D STo27 E STi30 F STi31 G STo28 H STo30 J D1 K D5 L D8 M D 10 N D 13 D 14 D 15 R/W DS A1 A2 A4 A5 A6 TMS TDO TC K D11 D 12 DTA CS A0 A3 A7 A8 A11 TD I TRST RESET D9 NC NC NC NC A9 A10 A12 A 13 D6 D7 GND VDD VDD VDD NC PLLVDD PLLGND NC F0i C LK D3 D4 VDD GND GND GND GND GND VDD NC NC ODE STo31 D2 VDD GND GND GND NC STi1 STi0 STo29 D0 VDD GND STi29 NC VDD GND GND VDD STo1 STi5 STi4 STi28 NC VDD GND GND GND GND GND VDD STo2 STi7 STi6 STo24 STo22 GND VDD VDD VDD VDD VDD GND STo3 STo6 STo4 STo23 STo19 STo18 STo17 STo16 STi15 STi14 STi13 STi12 STo7 STo5 STi25 S T o 21 S Ti 23 STi21 STi19 STi17 S To14 STo12 STo1 1 S To9 S Ti 11 STi8 STi24 STo20 STi22 STi20 STi18 STi16 STo15 STo13 STo10 STo8 STi10 STi9
TOP VIEW
GND
VDD
STo0
STi3
STi2
IC1
IC2
IC3
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- A1 corner is identified by metallized markings. 23mm x 23mm Ball Pitch 1.5mm
Figur e 3 - 160 Ball PBGA Pin Connections
Zarlink Semiconductor Inc.
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