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Details, datasheet, quote on part number:MT9196AS
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| Part: | MT9196AS |
| Category: | Communication => Telephony => Integrated Digital Phones |
| Description: | Description = Fully Featured Digital Telephone Circuit With Built-in Filter/CODEC, Digital Gain Pads, DTMF Generator, Tone Ringer, And Handset And Speakerphone Transducers ;; Package Type = Soic ;; No. Of Pins = 28 |
| Company: | Zarlink Semiconductor |
| Datasheet: | Download MT9196AS datasheet File size : 463 kB |
| Request For quote: | Find where to buy MT9196AS
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Datasheet text preview:
ISO2-CMOS MT9196 Integrated Digital Phone Circuit (IDPC)
Features
· · · · · · · · · · Program m a bl e µ-Law/A-Law CODEC and Filters Programma bl e CCITT (G.711)/sign-magnitude coding Programma bl e transmit, receive and side-tone gains Digital DTMF and single tone generation Fully differential interface to handset transducers Auxiliar y analog interface Interface to ST-BUS/SSI (compatible with GCI) Ser ial microport control Single 5 volt supply, low power operation Anti-howl circuit for group listening speakerphone applications
ISSUE 4
December 1995
Ordering Information MT9196AE 28 Pin Plastic DIP MT9196AP 28 Pin Plastic LCC MT9196AS 28 Pin SOIC -40°C to +85°C
Description
The MT9196 Integrated Digital Phone Circuit (IDPC) is designed for use in digital phone products. The device incorporates a built-in Filter/Codec, digital gain pads, DTMF generator and tone ringer. Complete telephony interfaces are provided for connecting to handset and speakerphone transducers. Internal register access is provided through a serial microport compatible with various industr y standard micro-controllers. The device is fabricated in Zarlink's ISO2-CMOS technology ensuring low power consumption and high reliability.
Applications
· · · Digital telephone sets Wireless telephones Local area communications stations
Digital Gain & Tone Generator VSSD VDD VSSA VSS SPKR VBias VRef 21/ - 24dB 3.0dB Tx & Rx
Filter/Codec Gain Encoder Decoder 7dB -7dB Transducer Interface
AUXin AUXout MIC + MM+
HSPKR + HSPKR Din Timing Dout STB/F0i CLOCKin Serial Microport XSTL2 IC IRQ CS DATA1 DATA2 SCLK Flexible Digital Interface SPKR + SPKR -
ST-BUS C&D Channels
WD
PWRST
Fi g u r e 1 - Functional Block Diagram
7-135
MT9196
M+ MVSSA MIC+ AUXin
VRef VBias
PWRST IC VSSD CS SCLK DATA1 DATA2
4 3 2 1 28 27 26 5 25 24 6 7 23 22 8 21 9 20 10 19 11 12 13 14 15 16 17 18
AUXout VSS SPKR SPKR+ SPKRHSPKR+ HSPKRVDD
WD IRQ Dout Din STB/F0i CLOCKin XSTAL2
MM+ VBias VRef PWRST IC VSSD CS SCLK DATA1 DATA2 WD IRQ Dout
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSSA MIC+ AUXin AUXout VSS SPKR SPKR+ SPKRHSPKR+ HSPKRVDD XSTAL2 CLOCKin STB/F0i Din
28 PIN PLCC
28 PIN SOIC/PDIP Figure 2 - Pin Connections
Pin Description
Pin # 1 2 3 4 5 6 7 8 9 10 Name MM+ VBias VRef PWRST IC VSSD CS SCLK DATA1 Description Inverting Microphone (Input). Inverting input to microphone amplifier from the handset microphone. Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier from the handset microphone. Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers. Connect 0.1 µF capacitor to VSSA. Reference voltage for codec (Output). Nominally [(VDD/2)-1.5] volts. Used internally. Connect 0.1 µF capacitor to VSSA. Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low). Internal Connection. Tie externally to VSS for normal operation. Digital Ground. Nominally 0 volts. Chip Select (Input). This input signal is used to select the device for microport data transfers. Active low. TTL level compatible. Serial Port Synchronous Clock (Input). Data clock for microport. TTL level compatible. Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/National mode of operation, this pin becomes the data transmit pin only and data receive is performed on the DATA2 pin. TTL level compatible input levels. Serial Data Receive. In Motorola/National mode of operation, this pin is used for data receive to the IDPC. In Intel mode, serial data transmit and receive are performed on the DATA1 pin and DATA2 is disconnected. Input level TTL compatible. Watchdog (Output). Watchdog timer output. Active high. Interrupt Request (Open Drain Output). Low true interrupt output to microcontroller. Data Output. A tri-state digital output for 8 bit wide channel data being sent to the Layer 1 device. Data is shifted out via this pin concurrent with the rising edge of BCL during the timeslot defined by STB, or according to standard ST-BUS timing. Data Input. A digital input for 8 bit wide channel data received from the Layer 1 device. Data is sampled on the falling edge of BCL during the timeslot defined by STB, or according to standard ST-BUS timing. Input level is CMOS compatible.
11
DATA2
12 13 14
WD
IRQ
Dout
15
Din
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MT9196
Pin Description (continued)
Pin # 16 Name STB/F0i Description Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit timeslot used by the device for both transmit and receive data. This active high signal has a repetition rate of 8 kHz. Standard frame pulse definitions apply in ST-BUS mode. CMOS level compatible input.
17
CLOCKin Clock Input. The clock provided to this input is used by the internal phone functions. In STBUS mode this is the C4i input. In SSI synchronous mode, this is the Bit Clock input. In SSI-asynchronous mode this is an asynchronous 4 MHz Master Clock input. XSTL2 VDD Crystal Input (4.096 MHz). Used in conjunction with the CLOCKin pin to provide the master clock signal via external crystal. Positive Power Supply (Input). Nominally 5 volts.
18 19 20 21 22 23 24 25 26 27 28
HSPKR- Inverting Handset Speaker (Output). Output to the handset speaker (balanced). HSPKR+ Non-Inverting Handset Speaker (Output). Output to the handset speaker (balanced). SPKRSPKR+ Inverting Speaker (Output). Output to the speakerphone speaker (balanced). Non-Inverting Speaker (Output). Output to the speakerphone speaker (balanced).
VSSSPKR Power Supply Rail for Speaker Driver. Nominally 0 Volts. AUXout AUXin MIC+ VSSA Auxiliary Port (Output). Access point to the D/A (analog) signals of the receive path as well as to the various analog inputs. Auxiliary Port (Input). An analog signal may be fed to the filter/codec transmit section and various loopback paths via this pin. No external anti-aliasing is required. Non-inverting on-hook answer back Microphone (Input). Microphone amplifier noninver ting input pin. Analog Ground (Input). Nominally 0 V.
7-137
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