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Details, datasheet, quote on part number:MT91L62AE
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| Part: | MT91L62AE |
| Category: | Multimedia => Audio => Codecs => Programmable Law |
| Description: | Description = 3V Single Rail Multi-featured Phone Codec With Programmable U/a Law Companding And Reference Voltage And Bias Source ;; Package Type = Pdip ;; No. Of Pins = 20 |
| Company: | Zarlink Semiconductor |
| Datasheet: | Download MT91L62AE datasheet File size : 321 kB |
| Request For quote: | Find where to buy MT91L62AE
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Datasheet text preview:
ISO2-CMOS MT91L62 3 Volt Single Rail Codec Advance Information
Features
· · · · · · · · · Single 2.7-3.6 volt supply Programma bl e µ-law/A-law Codec and filters Fully differential to output driver SSI digital interface Individua l transmit and receive mute controls 0dB gain in receive path 6dB gain in transmit path Low power operation ITU-T G.714 compliant
DS5179 ISSUE 4 August 1999
Ordering Information MT91L62AE MT91L62AS MT91L62AN 20 Pin Plastic DIP (300 mil) 20 Pin SOIC 20 Pin SSOP
-40°C to +85°C
Description
The MT91L62 3V single rail Codec incorporates a built-in Filter/Codec, transmit anti-alias filter, a reference voltage and bias source. The device suppor ts both A-law and µ-law requirements. The MT91L62 is a true 3V device employing a fully differential architecture to ensure wide dynamic range. An analog output driver is provided, capable of driving a 20k ohm load. The MT91L62 is fabricated in Zarlink's ISO2-CMOS technology ensuring low power consumption and high reliability.
Applications
· · · · Cellular radio sets Local area communications stations Line cards Batter y operated equipment
FILTER/CODEC GAIN VDD VSSA VBias VRef AIN+ ENCODER DECODER 6dB 0 dB Analog Interface AIN-
AOUT + AOUT -
Din Dout STB CLOCKin PCM Serial Interface
Timing
Control
PWRST
IC
A/µ
CSL0
CSL1 CSL2 RXMute TXMute
Fi g u r e 1 - Functional Block Diagram
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MT91L62
Advance Information
VBias VRef PWRST IC A/µ RXMute TXMute CSL0 CSL1 CSL2
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
AIN+ AINVSS AOUT + AOUT VDD CLOCKin STB Din Dout
20 PIN PDIP/SOIC/SSOP Figure 2 - Pin Connections
Pin Description
Pin # 13 14 15 16 17 18 19 20 21 22 23 Name VBias VRef Description Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers. Connect 0.1 µ F capacitor to VSS. Reference Voltage for Codec (Output). Nominally [(VDD/2)-1.1] volts. Used internally. Connect 0.1 µ F capacitor to VSS. Internal Connection. Tie externally to VSS for normal operation. A/µ Law Selection. CMOS level compatable input pin governs the companding law used by the device. A-law selected when pin tied to VDD or µ-law selected when pin tied to VSS.
PWRST Power-up Reset. Resets internal state of device via Schmitt Trigger input (active low). IC A/µ
RXMute Receive Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal operation. CMOS level compatable input. TXMute Transmit Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal operation. CMOS level compatable input. CSL0 CSL1 CSL2 Dout Clock Speed Select. These pins are used to program the speed of the SSI mode as well as the conversion rate between the externally supplied MCL clock and the 512 KHz clock required by a filter/codec. Refer to Table 2 for details. CMOS level compatable input. Data Output. A tri-state digital output for 8-bit wide channel data being sent to the Layer 1 device. Data is shifted out via the pin concurrent with the rising edge of BCL during the timeslot defined by STB. Data Input. A digital input for 8-bit wide data from the layer 1 device. Data is sampled on the falling edge of BCL during the timeslot defined by STB. CMOS level compatable input. Data Strobe. This input determines the 8-bit timeslot used by the device for both transmit and receive data. This active high signal has a repetition rate of 8 kHz. CMOS level compatable input.
24 13
Din STB
14
CLOCKin Clock (Input). The clock provided to this input pin is used by the internal device functions. Connect bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this pin when the bit clock is 128 kHz or 256 kHz. CMOS level compatable input. VDD AOUTAOUT+ VSS AinAin+ Positive Power Supply. Nominally 3 volts. Inverting Analog Output. (balanced). Non-Inverting Analog Output. (balanced). Ground. Nominally 0 volts. Inverting Analog Input. No external anti-aliasing is required. Non-Inverting Analog Input. Non-inverting input. No external anti-aliasing is required.
15 16 17 18 19 20
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Advance Information
Overview
The 3V Single-Rail Codec features complete Analog/ Digital and Digital/Analog conversion of audio signals (Filter/Codec) and an analog interface to a standard analog transmitter and receiver (analog Interface). The receiver amplifier is capable of driving a 20k ohm load.
MT91L62
Companding law selection for the Filter/Codec is provided by the A/µ companding control pin. Table 1 illustrates these choices. ITU-T (G.711) µ-Law
1000 0000 1111 1111 0111 1111 0000 0000
Code
+ Full Scale + Zero
A-Law
1010 1010 1101 0101 0101 0101 0010 1010
Functional Description
Filter/Codec The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are programmable. These are ITU-T G.711 A-law or µ-Law, with true-sign/Alternate Digit Inversion. The Filter/Codec block also implements a transmit audio path gain in the analog domain. Figure 3 depicts the nominal half-channel for the MT91L62. The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide dynamic range from a single 3 volt supply design. This fully differential architecture is continued into the Analog Interface section to provide full chip realization of these capabilities for the external functions. A reference voltage (VRef), for the conversion requirements of the Codec section, and a bias voltage (VBias), for biasing the internal analog sections, are both generated on-chip. VBias is also brought to an external pin so that it may be used for biasing external gain setting amplifiers. A 0.1µF capacitor must be connected from VBias to analog ground at all times. Likewise, although VRef may only be used internally, a 0.1µF capacitor from the VRef pin to ground is required at all times. The analog ground reference point for these two capacitors must be physically the same point. To facilitate this the VRef and VBias pins are situated on adjacent pins. The transmit filter is designed to meet ITU-T G.714 specifications. An anti-aliasing filter is included. This is a second order lowpass implementation with a cor ner frequency at 25 kHz. The receive filter is designed to meet ITU-T G.714 specifications. Filter response is peaked to compensate for the sinx/x attenuation caused by the 8 kHz sampling rate.
-Zero (quiet code) - Full Scale
Table 1: Law Selection An a l o g Interfaces Standard interfaces are provided by the MT91L62. These are: · T h e analog inputs (transmitter), pins AIN+/AIN-. T h e maximum peak to peak input is 2.123Vpp µ-law across AIN+/AINand 2.2Vpp A-law a c r o s s these pins. · T h e analog outputs (receiver), pins AOUT+/ AO UT- . T h is internally compensated fully d if fe r e n t ia l output driver is capable of driving a lo a d of 20k ohms. PCM Serial Interface A serial link is required to transport data between the MT91L62 and an external digital transmission device. The MT91L62 utilizes the strobed data interface found on many standard Codec devices. This interface is commonly referred to as Simple Serial Interface (SSI). The bit clock rate is selected by setting the CSL2-0 control pins as shown in Figure 2. Q u ie t Code The PCM serial port can be made to send quiet code to the decoder and receive filter path by setting the RxMute pin high. Likewise, the PCM serial port will send quiet code in the transmit path when the
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