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Details, datasheet, quote on part number:MT92220BG
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| Part: | MT92220BG |
| Category: | Communication => Telephony => Voice over IP |
| Description: | Description = 1023 Channel Voice Over IP/AAL2 Processor ;; Package Type = Epbga ;; No. Of Pins = 608 |
| Company: | Zarlink Semiconductor |
| Datasheet: | Download MT92220BG datasheet File size : 2802 kB |
| Request For quote: | Find where to buy MT92220BG
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Datasheet text preview:
MT92220 1023 Channel Voice Over IP/AAL2 Processor
Data Sheet F ea t u r e s
· · · · · · · · · · · · 1023 full-duplex PCM or ADPCM voice channels over IP/UDP/RTP connections or over AAL2 VCs Simultaneously support of IP/UDP connection and AAL2 VC RTP packaging optional in IP/UDP connection Supports IP version 4 and version 6 Supports IP over Ethernet, ATM (AAL5) or POS Support Ethernet II, IEEE 802.3, LLC/SNAP and PPP frames Supports Classical IP over ATM and LAN Emulation (LANE) v1/v2 Supports MPLS, MPOA and IEEE 802.1p/Q ELAN-ID Packages voice in AAL2 according to I.363.2 and I.366.2 H.110 compliant TDM bus carrying PCM, ADPCM or HDLC channels HDLC channels can be used to carry UDP payload or AAL2 CPS-packet generated by external agent Support trunking in RTP and AAL2; up to 255 PCM/ADPCM channels per RTP connection or
MT9043 MT9041 DS5828 Issue 3 December 2002
Ordering Information MT92220 6 0 8 P in EPBGA
-40 °C to +85°C AAL2 CID Support maximum 1500 bytes packet size Up to 4096 bytes of jitter buffer, absorbing +/- 256 ms of PDV Less than 250 usec of latency Injection of CPU-generated RTP or AAL2 CPSpackets Reception of CPU-destinated RTP or AAL2 CPSpackets Primary and secondary network interfaces Primary network interface supports 10/100 MII, POS-PHY or Utopia level 1/2 Secondary network interface supports Utopia level 1
· · · · · · · ·
(8K to16.384M PLL)
optional
Intel/Motorola CPU
MT92220 Message Channel H0 H.110 Signals Compatibility Clocks and Frame Pad H100/ H110 Interface C lo c k Recovery uP Interface Second Network Interface Primary Network Interface UTOPIA Port B (PHY/SAR) MII, POS, or UTOPIA (PHY/SAR) interface
Service Timer
SS
RTP/AAL2 Assembly RTP/AAL2 D is a s s e m b l y
TDM DataPath
SS/Padding Calculator
Packet Identification and Routing
Dual Memory Controler
Network Memory Controler
SSRAM (256k x18*) Memory Bank A
SSRAM (512k x18*) Memory Bank B
SSRAM (256k x36*)
SDRAM (4M x32*)
Memory Bank C
*Typical RAM size for the support of 1023 channels. Parity bis are optionnal on all memories.
F i g u r e 1 - MT92220 Block Diagram
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MT92220
· · · Proprietary Adaptive Silence Suppression Less than 2.5 watts of power 608 pin PBGA package
Data Sheet
A pp l i ca t io n s
· · · · · · High density voice gateway Voice over IP and/or AAL2 3G and UMTS Network processor IP and/or AAL2 switching Voice over DSL/cable
D e sc r i pt i on
The MT92220 device is a voice over IP/RTP assembly and disassembly engine that can convert up to 1023 fullduplex PCM voice channels or 4096 HDLC channels to IP packets and back, conforming to IETF RFC791 (IPv4), RFC2460 (IPv6), RFC768 (UDP) and RFC1889 (RTP). It can also perform AAL2 encapsulation and deencapsulation conforming to ITU I.363.2. On one side, the device communicates with an H.110 TDM bus carrying voice in either PCM format, ADPCM or HDLC-encapsulated mini-packets; on the other side, it carries its packet data over Ethernet, ATM (using AAL5 cells) or Packet over SONET or, in the case of AAL2, over ATM. A 16-bit Intel/Motorola CPU interface is used to access and configure the device. Finally, three external SSRAM banks and one external SDRAM bank are used for configuration and storage space.
Conventions
In this document, the following conventions are used: · · · · · · · · · · · · · The transmission direction and the abbreviation TX always refer to the direction in which voice is converted into IP packets or AAL2 cells. The reception direction and the abbreviation RX refer to the direction in which packets or cells are converted into PCM bytes or HDLC packets. All numbers in this document are decimal unless otherwise specified. Hexadecimal number can be identified by the `h' suffix (ex: A5h). Binary numbers are either in double quotes for multiple bits or in single quotes for individual bits (ex: "1001", `0'). The term "byte" means 8 bits. The term "word" means 16 bits. The term "dword" means 32 bits. The word "high" means a binary value of `1'. The word "low" means a binary value of `0'. The verb "to clear" means to reset one or multiple bits to `0' The verb "to set" means to put one or multiple bits to `1'. All addresses are specified in hexadecimal and point to bytes. Addresses are converted from bytes to words to double words using the little endian format, unless otherwise specified.
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Zarlink Semiconductor Inc.
Data Sheet
Color Code
In this document, the following color code is used: · · ·
MT92220
Fields in red are initialized by software when the structure is created, and are written back by the hardware. Fields in black are initialized by software when the structure is created, and are never written back by the hardware. Fields in dark yellow are initialized by software when the structure is created and are written back at the same value by the hardware. This shade denotes a Reserved Field. This shade denotes an Unimplemented Field. The field outlined in red is only written back by the chip when one of the bits, contained within the field and in red, was set and will then be cleared by the chip when it is done acting upon the set request bit.
Document Organization
This data sheet is divided into the following sections: · · · · · · · · · · · · · CPU Interface (Chapter 2.0) describes the main external interface of the MT92220 chip. Network Interface (Chapter 3.0) describes the interface to the 3 different types of link interfaces, Ethernet, UTOPIA, and Packet over SONET, that are supported. Link Layers (Chapter 4.0) describes the 3 different types of link layers, Ethernet, ATM AAL5, and Packet over SONET, that are supported. RX/TX Data Flows (Chapter 5.0) describes the data flows for all packets received and transmitted. Packet Identification (Chapter 6.0) describes the process by which packets are identified. TX/RX AAL2 VC Treatment (Chapter 7.0) describes the treatment of AAL2 mini-packets and cells as they are transmitted and received from the network. Packet Assembly (Chapter 8.0) describes the collected bytes written in the circular buffers by the TX TDM, and how they are assembled into RTP or AAL2 packets. Packet Disassembly (Chapter 9.0) describes how RTP and AAL2 packets are transformed into PCM bytes, ADPCM samples, or HDLC/CPU-destined mini-packets. TX/RX TDM Data Paths (Chapter 10.0) describes the data paths for all bytes transmitted and received with the H.110 interface. H.110 Interface (Chapter 11.0) describes the compatibility of the TDM interface with the H.110 bus. Clocking (Chapter 12.0) describes the clocks used for the Network Interface and the SAR portion of the device. Pin-out is in Chapter 13.0. Electrical Characteristics (Chapter 14.0) describes the electrical characteristics of all the interfaces.
Register List and Memory Map are contained in the MT92220 Design Manual.
Zarlink Semiconductor Inc.
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