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Details, datasheet, quote on part number:MV1403
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Datasheet text preview:
MV1403
ADVANCE INFORMATION
DS3046-2.1
MV1403
PCM MACROCELL DEMONSTRATOR
The MV1403 contains 8 PCM macrocells which can be configured so as to perform the common channel signalling and error detection functions for a 2.048 Mbit 30 channel PCM t r a n s m i s s i o n link, operating to the appropriate CCITT recommendations. The MV1403 also allows access to all the macrocells individually and is implemented in GPS CMOS technology utilising the CLA60000 series gate array, offering high performance, low power and fast turn-round. The following macrocells are included in the MV1403. Timeslot Zero Transmitter - TXTSZ Timeslot Sixteen Transmitter - TXTS16 Cyclic Redundancy Check Generator - CRCGEN High Density Bipolar (HDB) 3 Encoder - HDB3EC Timeslot Zero Receiver - RXTSZ Timeslot Sixteen Receiver - RXTS16 Cyclic Redundancy Checker - CRCCHK High Density Bipolar (HDB) 3 Decoder - HDB3DC W i t h the MV1403 set up to combine the internal macrocells, two demonstration modes are available, referred to as Transmit and Receive demonstration modes. In Transmit demonstration mode, timeslot zero sync word (including user data bits and optional CRC check bits), timeslot sixteen data and 30 voice channels are combined and transmitted as pseudo-ternary HDB3 encoded outputs. The Transmit demonstration mode can also be set to generate C R C multiframe data in accordance with CCITT Recommendation G. 704. In Receive demonstration mode, the pseudo-ternary HDB3 i n p u t s are decoded back to NRZ form and frame synchronisation is achieved by detection of the Frame Alignment signal in the incoming data stream. This permits extraction of user data bits, timeslot sixteen data and voice c h a n n e l data. An optional CRC mode generates CRC multiframe alignment and a cyclic redundancy check is carried out on the incoming data. In addition receive demonstration mode generates appropriate alarms for loss of input, double violation on the HDB3 inputs, loss of frame or CRC multiframe alignment, detection of erroneous frame alignment word, remote alarm received from the transmitter, and detection of a CRC error in either submultiframe 1 or 2.
VDD1 ER MFQ1 MFQ2 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ1 Q1S VDD2 GND1 LIA MFQ3 MFQ4 MFQ5 FRS13RZ MFD1 MFD2 MFD3 MFD4 VDD3
1 2 3 4 5 6 7 8 9 10
48 47 46 45 44 43 42 41 40
GND4 CCR CK8 TZSRZ TSZRZ MFQ9 FRS13 FRS15 MFQ8 MFQ7 MFQ6 RST GND3 MFD6 TZS FRS MFD5 CRC P STM CLK MODE DEMO GND2
MV 39 1403 11 DP 38
12 13 14 15 16 17 18 19 20 21 22 23 24 37 36 35 34 33 32 31 30 29 28 27 26 25
DP48
13 GND1
17 MFQ5
16 MFQ4
15 MFQ3
DQ1
10 DQ3
DQ4
DQ5 8
12 Q1S
14 LIA
11
9
FRS13RZ MFD1 MFD2 MFD3 MFD4 VDD DEMO MODE CLK STM P
18 19 20 21 22 23 24 25 26 27 28
PIN 1 IDENT
7
DQ6
6 5 4 3 2
DQ7 DQ8 MFQ2 MFQ1 ER GND2 CCR CK8 TZSRZ TSZRZ MFQ9
MV 1403 HP
1 44 43 42 41 40
29
30
31
32
33
34
35
36
37
38
39
HP44
CRC
MFD5
FRS
TZS
MFD6
MFQ6
MFQ7
MFQ8
FRS15
NOTE:
MFD is multi-function input, MFQ is multi-function output
Figure 1: Pin connections - top view
s Transmitted Frame Structure to CCITT Recommendation G. 704 s Receiver Frame Synchronisation to CCITT s Recommendation G. 732 s Selectable CRC Mode s CRC Generation and Checking to CCITT Recommendation G. 704
FEATURES
s s s s s Single + 5V Supply All Inputs and Outputs TTL Compatible Selectable as PCM Transmitter or Receiver Allows Access to all 8 Macrocells Individually HDB3 Encoding and Decoding to CCITT Recommendation G. 703
FRS13
RST
1
MV1403
FUNCTIONAL DESCRIPTION
The MV1403 PCM macrocell demonstrator contains a family of 4 Transmit PCM and 4 Receive PCM macrocells which may be configured to function individually, or be connected together to form demonstrations of their operation. In order to keep the pin count to a minimum, some of the input and output pins are shared. Pin functions thus depend upon whether the device is configured as a transmitter or receiver. The operational modes of the MV1403 are selected under control of the MODE and DEMO pins, as shown in Table 1. Note that the MODE pin selects either the transmit or receive set of macrocells and that the DEMO pins selects either individual or combined connections. In addition the operation of the MV1403 is controlled by a further two control inputs, STM and CRC. The STM pin is used for device testing and should be tied low for normal operation. The CRC control pin selects whether or not the deviceperforms the CRC generation/checking procedure. A logic High' on this pin puts the device in Cyclic Redundancy Generate/Check mode. More detailed information about all 8 macrocells can be found in the individual macrocell publications. INDIVIDUAL TRANSMIT MODE, TX1 In this mode (MODE = 0, DEMO = 0) the four transmitter macrocells (TXTSZ, TXTS16, CRCGEN and HDB3EC) are all accessed individually. The functional diagram of the MV1403 in this mode is shown in Fig. 2. All four macrocells are synchronised to a common 2.048MHz clock, and the TXTSZ, TXTS16 and CRCGEN macrocells are also synchronised to a second timing input, FRS (Frame Sync). This is an 8 clock period high going pulse at 8kHz which masks timeslot zero to enable frame alignment. The function of each transmit macrocell is now described separately. TIMESLOT ZERO TRANSMITTER The Timeslot Zero Transmitter macrocell generates a Frame Alignment Signal (FAS) in accordance with CCITT R e c o m m e n d a t i o n G. 704. This is combined with the international spare bit (the D1 input) and output on Q during timeslot zero of alternate frames, denoted sync frames. During the other interleaved frames, denoted non-sync frames, bit 2 is fixed at logic 1 to avoid imitation of the FAS. This bit is slotted together with the international spare bit (D1 input) and 6 user data bits (the D3N-D8N inputs) for output on Q. A TZS output (Timeslot Zero Sync frame) is provided to denote whether a sync frame or non-sync frame is being output. It changes state one clock period after the end of timeslot zero and is high during timeslot zero of sync frames. Fig. 3 shows the timing diagram for this macrocell. TIMESLOT SIXTEEN TRANSMITTER This macrocell takes in a continuous 64kbit data stream (D input) and outputs it in 8 bit packets at a bit rate of 2.048 Mbit during timeslot 16 of successive frames on its Q output. The position of timeslot 16 is determined from the FRS timing input, which masks timeslot zero. The TS16 output is an 8 clock period high going pulse at 8kHz, similar to FRS, but high during the 8 bits of timeslot sixteen. Fig. 4 shows the timing diagram for this macrocell. CYCLIC REDUNDANCY CHECK GENERATOR This macrocell has two modes of operation, selected by its EN control input. When EN is `high', CRC generation mode is selected. However, both modes are concerned with producing the data bit to be inserted into the international spare bit of timeslot zero (CCITT G. 704 structure). In non-CRC mode, this data is selected to be either the D1S (sync frames) or DlN (non-sync frames) input depending upon whether a sync or non-sync frame is about to be transmined (determined by the TZS input). With CRC mode enabled, the macrocell generates CRC words and outputs this data during the international spare bit of s y n c frames. During non-sync frames, the 6 bit CRC Multiframe Alignment Signal is output along with the two user data inputs, DlS and D1N. This procedure is carried out in accordance with CCITT Recommendation G. 704. The CRC word is generated from the incoming data stream on the D input pin. CCITT Recommendation G. 704 defines the 16 frame CRC multiframe structure, not related to the possible use of a 16 frame multiframe structure in timeslot 16. Each 16 frame CRC multiframe is divided into two 8 frame submultiframes, denoted submultiframes 1 and 2 (SMF1 and SMF2). The CRC procedure is carried out on each submultiframe of data and the resulting 4 bit CRC word is output during the international spare bit of sync frames during the following sub-multiframe. All data is output on the Q output pin. Table 2 displays the CRC multiframe structure in more detail . HIGH DENSITY BIPOLAR (HDB3 )ENCODER The HDB3 Encoder macrocell converts the incoming NRZ data on its D input pin into HDB3 pseudo-ternary form for transmission over a 2.048 Mbit PCM link in accordance with C C I T T Recommendation G.703. The two TXD outputs represent the HDB3 data in pseudo-ternary form. They are always low during the high half cycle of CLK, but may be high or low during the low half cycle. The Q output represents the D input but delayed by one period. Fig. 5 shows the timing diagram of this macrocell.
2
MV1403
FRS DQ1, DQ3-DQ8 D1, D3N-D8N Q MFQ2 MFQ1 MFD6 D Q MFQ9 MFQ8 TS16
FRS
TXTSZ
TZS STM DEMO MODE CLK CLK
TXTS16
MODE CONTROL
TXD1 CRC EN (CRC)
MFQ5 MFQ4
CRCGEN
D TZS D1S D1N MFD5
Q D
HDB3EC
Q MFQ3
TXD2
VDD GND
TZS MFD4 MFD2 MFQ6
MFD3
Figure 2: TX1 Individual Transmit mode functional diagram
Mode Name
MODE input
DEMO input
CRC input
STM input
Mode description
TX1 TX2 RX1 RX2 TX1/2 TX1/2 RX1/2 RX1/2 -
0 0 1 1 0 0 1 1 X
0 1 0 1 0/1 0/1 0/1 0/1 X
0/1 0/1 0/1 0/1 0 1 0 1 X
0 0 0 0 0 0 0 0 1
MV 1403 is configured as individual Transmit PCM macrocells MV1403 is configured as a PCM Transmitter demonstration, using the Transmit macrocells MV1403 is configured as individual Receive PCM macrocells MV1403 is configured as a PCM Receiver demonstration, using the Receive macrocells CRC generation mode of the CRCGEN macrocell is disabled CRC generation mode of the CRCGEN macrocell is enabled CRC mode of the RXTSZ macrocell is disabled CRC mode of the RXTSZ macrocell is enabled MV1403 is configured in device test mode. This mode should not be used for normal operation
Table 1: Operational modes of the MV1403
CRC Multiframe Sub-Multiframe 1 (SMF1) Frame number Bit one of timeslot zero 0 1 2 C2 3 0 4 C3 5 1 6 C4 7 0 8 C1 Sub-Multiframe 2 (SMF2) 9 1 10 C2 11 1 12 C3 13 D1S 14 C4 15 D1N
C1 0
NOTES: 1. C1, C2, C3, C4 are the bits of the CRC word. 2. 001011 is the CRC Multiframe Alignment Signal (MAS). 3. Even numbered frames are denoted Sync frames; odd numbered frames are denoted non-sync frames.
Table 2: Structure of the CCITT CRC Multiframe
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