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Details, datasheet, quote on part number:MV1443
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Datasheet text preview:
THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
MV1443
PRELIMINARY INFORMATION
DS3107 2.2
MV1443
PCM TIMESLOT ZERO TRANSMITTER AND RECEIVER
The MV1443 combines the Timeslot Zero Transmitter and Receiver functions required by a 2.048Mbit 30 channel PCM transmission link operating in accordance with the appropriate CCITT Recommendations and forms part of the GPS 2Mbit PCM signalling series of devices. The circuit is fabricated in CMOS and operates from a single +5V supply with all inputs and outputs being TTL compatible. The Timeslot Zero Transmitter half of the circuit is responsible for generating the timeslot zero synchronising w o r d of a 2Mbit PCM link in accordance with CCITT Recommendation G.704. This function is performed by alternately generating sync frames, containing the CCITT Frame Alignment Signal, and non-sync frames containing user data bits. The Timeslot Zero Receiver function searches for the CCITT Frame Alignment signal in the incoming data stream and when this is present the receiver synchronises itself to this pattern in accordance with the Frame Alignment strategy detailed in CCITT Recommendation G.732. Once frame alignment has been achieved the Timeslot Zero Receiver produces various timing outputs for the use of external circuitry and extracts the user data bits of timeslot zero.
GND1 RST D TZS-RZ NC Q1N Q1S FRS Q CLK-TZ D8N D7N D6N D5N D4N D3N D1N D1S TZS-TZ GND2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32
VDD CLK-RZ NC Q8N Q7N Q6N Q5N Q4N Q3N CRC SA ER RAI FRS15 FRS13 NC CK8 CCR STM TSZ
MV 31 1443
30 29 28 27 26 25 24 23 22 21
DG40, DP40
FEATURES
VDD Q8N Q7N Q6N Q5N Q4N Q3N CRC SA ER RAI FRS15 FRS13 NC 38 37 36 35 34 33 32 31 30 NC RST
NC
NC
s Transmitter generates Frame Alignment Signal in accordance with CCITT Recommendation G.704. s Enables access to User Data Bits of Timeslot Zero. s Receiver Frame Synchronisation carried out in accordance with CCITT Recommendation G.732. s Provides Alarm Outputs for Reception of Corrupted Alignment word and Loss of Frame Alignment. s Extracts the International Spare Bits from Alternate Frames or from Frames 13 and 15 of the CCITT CRC multiframe.
6 NC Q1N Q1S FRS Q CLK-TZ D8N D7N D6N D5N D4N 7 8 9 10 11 12 13 14 15 16
5
4
3
2 1
44 43 42 41 40 39
MV 1443
17 29 18 19 20 21 22 23 24 25 26 27 28 TZS-TZ GND2 TSZ STM CCR D3N D1N D1S CK8 NC
ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings are limiting values above which operating life may be shortened or specified parameters may be degraded.
NC
D
s All Inputs and Outputs TTL compatible.
CLK-RZ
TZS-RZ
s Single +5V supply.
GND1
HG44, HP44
Fig. 1 Pin connections - top view
ELECTRICAL RATINGS
Supply Voltage Input Voltage Output Voltage -0.5V to +7V -0.5V to VDD +0.5V -0.5V to VDD +0.5V
1
MV1443
D8N
D6N
D7N
D5N
D4N
D3N
Q
TZS-TZ
ER
SA
RAI
D1S
Timeslot Zero Transmitter
Q8N Q7N Q6N Q5N Q4N
D1N
CLK-TZ FRS
Timeslot Zero Receiver
Q3N Q1N Q1S
TSZ TZS-RZ CCR CK8
VDD
GND1
GND2
STM
Fig. 2 Block diagram
CLK-RZ
D
RST
FRS15 FRS13 CRC
FUNCTIONAL DESCRIPTION
The MV1443 combines the Timeslot Zero Transmitter and Receiver functions required by a 2.048Mbit 30 channel PCM transmission link operating in accordance with the appropriate CCITT Recommendations. The block diagram of the MV1443 is shown in Fig.2 and the function of each block is now described separately. Timeslot Zero Transmitter The Timeslot Zero Transmitter circuit generates the timeslot zero synchronising word required by a 2.048Mbit PCM link in accordance with CCITT Recommendation G.704. During alternate frames, denoted sync frames, the CCITT Frame Alignment Signal (FAS - 0011011) is combined with the International / CRC data bit input, D1S, for bit 1 and injected on to the PCM highway via the Q output. During the other interleaved frames, denoted non-sync frames, bit 2 of timeslot zero is set to `1' to avoid imitation of the FAS and this is combined with the second International / CRC data bit, D1N, for bit 1 and the user data bits, D3N-D8N, for bits 3 to 8, and again injected on to the PCM highway. In order to perform this function the Timeslot Zero Transmitter requires 2 timing inputs in addition to the parallel data bit inputs, pins CLK-TZ and FRS. The CLK-TZ input is a 2.048MHz clock input whilst FRS is a high going pulse, 8 clock periods long, which is required to mask timeslot zero of each frame. In addition to the PCM data stream output the Timeslot Zero Transmitter produces a timing output, TZS-TZ, which changes state one clock period after the end of Timeslot Zero and is high during the transmission of timeslot zero of sync frames.
The timing diagram of the Timeslot Zero Transmitter circuit is shown in Fig.3. Timeslot Zero Receiver The Timeslot Zero Receiver circuit is responsible for searching for and locking on to the CCITT Frame Alignment Signal present in timeslot zero of the PCM data stream being clocked in to its D input. This process is carried out in accordance with the loss and recovery of frame alignment strategy described in CCITT Recommendation G.732. Once frame alignment has been achieved the Timeslot Zero Receiver circuit outputs various timing reference signals for the synchronisation of external circuitry. These timing outputs will all free run if frame synchronisation is subsequently lost. In addition, a control input, RST, may be used to reset this synchronisation process, forcing the receiver out of frame alignment. The Timeslot Zero Receiver circuit produces 4 timing outputs for use by external circuitry if required. The first of these timing outputs is TSZ which is an 8 clock period long, high going pulse masking the position of timeslot zero, similar to the FRS input of the Timeslot Zero Transmitter, and facilitates the frame alignment of external circuitry. The second timing output, TZS-RZ, is a 4KHz signal which changes state once per frame, one clock period after the end of timeslot zero, and is high during sync frames to allow sync and non-sync frames to be distinguished. The third timing output, CCR, is a low going pulse, one clock period wide, occurring during 1 bit, timeslot 1 of sync frames. The final timing output, CK8, is an 8KHz signal going low at the end of bit 7 of each timeslot zero and high at the end of bit 7 in each timeslot 16.
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