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Details, datasheet, quote on part number:MV1449
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Datasheet text preview:
THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
MV1449
PRELIMINARY INFORMATION
DS3164 2.2
MV1449
PCM HDB3 ENCODER/DECODER
The MV1449, along with other devices in the GPS 2Mbit PCM signalling series comprise a group of circuits which will perform the common channel signalling and error detection functions for a 2.048Mbit PCM transmission link operating in accordance with the appropriate CCITT Recommendations. The MV1449 is also capable of operation at the next CCITT hierarchical bit rate of 8.448Mbit. The MV1449 circuit is fabricated in CMOS and operates from a single +5V supply with all inputs and outputs being TTL compatible. The MV1449 is an encoder/decoder for the HDB3 pseudoternary transmission code, described in Annex A of CCITT Recommendation G.703. The device encodes and decodes s i m u l t a n e o u s l y and asynchronously. Error monitoring functions are provided to detect violations of the HDB3 coding, all ones detection and loss of input (all zero's detection). In addition a loop back function is provided for terminal testing.
D CLK-EC LIA Q CLK-DC RESET AIS AIS GND
1 2 3 4 5 6 7 8
16 15 14 MV 13 1449 12 11 10 9
VDD TXD2 TXD1 RXD2 LTE RXD1 CDR DV
FEATURES
s Single +5V supply. s All Inputs and Outputs TTL compatible. s HDB3 Encoding and Decoding to CCITT Recommendation G.703. s Simultaneous Encoding and Decoding. s Clock Recovery Signal allows Clock Regeneration from Incoming HDB3 Data. s Loop Back Control. s HDB3 Error Monitor. s Alarm Indication Signal Monitor. s Loss of Input Alarm. s Low Power Operation. s 2.048MHz or 8.448MHz Operation.
DG16, DP16
D CLK-EC LIA Q CLK-DC RESET AIS AIS GND
1 2 3 4
16 15 14
VDD TXD2 TXD1 RXD2 LTE RXD1 CDR DV
MV 13 1449 5 12 6 7 8 11 10 9
MP16/L
Fig. 1 Pin connections - top view
ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings are limiting values above which operating life may be shortened or specified parameters may be degraded.
ELECTRICAL RATINGS
Supply Voltage Input Voltage Output Voltage -0.5V to +7V -0.5V to VDD +0.5V -0.5V to VDD +0.5V
ORDERING INFORMATION
MV1449/IG/DGAS MV1449/IG/DPAS MV1449/IG/MPES
1
MV1449
RXD2 RXD1
TXD1
TXD2
RESET AIS
AIS
D
CLK-EC
HDB3 Encoder
HDB3 Decoder, Error and AIS Circuits
Q DV LIA
VDD GND
LTE
CDR
CLK-DC
Fig. 2 Block diagram
FUNCTIONAL DESCRIPTION
High Density Bipolar 3 (HDB3) is a ternary transmission code in which the number of consecutive zeros which may occur is restricted to three, to ensure adequate clock recovery at the receiver. In any sequence of four consecutive binary zero's, the last zero is substituted by a mark of the same polarity of the previous mark, thus breaking the Alternate Mark Inversion (AMI) code. This mark is termed a violation. In addition, the first zero may also be substituted by a mark if the last mark and last violation are of the same polarity. This mark does not violate the AMI code and ensures that successive violations alternate in polarity and as such introduce no DC component to the HDB3 signal. The MV1449 consists of two main blocks, the HDB3 Encoder and the HDB3 Decoder, with the Block Diagram being shown in Fig. 2. The function of each block is now described separately. HDB3 Encoder The HDB3 Encoder is responsible for converting the incoming NRZ data into HDB3 Encoded pseudo-ternary form for transmission over a 2.048Mbit/8.448Mbit PCM link. This conversion is carried out in accordance with the HDB3 coding laws specified in CCITT Recommendation G.703, Annex A. The data to be encoded is input on the D input pin and the encoding process is synchronised to the 2.048MHz/8.448MHz clock signal being input on the CLK-EC pin. The HDB3 Encoder has two outputs, TXD1 and TXD2, which represent the HDB3 encoded PCM data stream in pseudo-ternary form. If a mark or violation is to be transmitted the output pulses high after the rising edge of clock, with the length of the pulse set by the clock high pulse width. The timing diagram of the HDB3 Encoder is shown in Fig. 3.
HDB3 Decoder The HDB3 Decoder circuit is responsible for converting the 2.048Mbit/8.448Mbit HDB3 encoded pseudo-ternary PCM data stream on its inputs, RXD1 and RXD2, into NRZ binary form to be output on the Q output pin. This conversion is carried out in accordance with the HDB3 coding laws specified in CCITT Recommendation G.703, Annex A. The HDB3 Decoder synchronously decodes the data on its RXD input pins into NRZ form under control of the 2.048MHz/8.448MHz clock being input on its CLK-DC pin. There is a 5 clock period delay between the HDB3 data being clocked in from the RXD inputs and the NRZ data appearing on the Q output. The Decoder clock must be externally regenerated from the incoming HDB3 data stream and in order to aid this clock recovery a logical `OR' function of the inverted HDB3 inputs is output on the CDR pin. In addition to the basic HDB3 decoding the circuit also provides three alarm outputs. The first of these alarms is DV (Double Violation) and a logic high on this output denotes that two successive violations have been received with the same polarity, thus violating the HDB3 decoding laws. The second alarm, LIA (Loss of Input Alarm), is used to denote that 11 consecutive zero's have been received on the RXD inputs. The third alarm output is AIS (Alarm Indication Signal). This output will go high if less than 3 decoded zero's have been detected in the preceding RESET AIS=1 period (i.e. between RESET AIS=0 pulses) and as such this alarm can be used to detect the CCITT Alarm Indication Signal. All the alarm circuitry as well as the decoding process is synchronised to the clock signal being input on the CLK-DC pin. The clock signal may be asynchronous with the CLK-EC signal. The timing diagrams of the HDB3 Decoder circuit are shown in Fig. 4. In addition to the normal mode of operation, a loop test mode is available for terminal testing. This mode is selected by taking the LTE (Loop Test Enable) input high. In this mode, the HDB3 encoded pseudo-ternary data outputs of the encoder block are inverted and fed back as the inputs to the decoder block, which in turn decodes this data and outputs it in NRZ form.
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