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Details, datasheet, quote on part number:NJ8820MPTF
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Datasheet text preview:
THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
NJ8820
DS3277-1.2
NJ8820
FREQUENCY SYNTHESISER (PROM INTERFACE)
The NJ8820 is a synthesiser circuit fabricated on the GPS CMOS process and is capable of achieving high sideband attenuation and low noise performance. It contains a reference oscillator, 11-bit programmable reference divider, digital and sample-and-hold comparators, 10-bit programmable `M' counter, 7-bit programmable `A' counter and the necessary control and latch circuitry for accepting and latching the input data. Data is presented as eight 4-bit words read from an external memory, with the necessary timing signals generated internally. It is intended to be used in conjunction with a two-modulus prescaler such as the SP8710 series to produce a universal binary coded synthesiser. The NJ8820 is available in Plastic DIL (DP) and Miniature Plastic DIL (MP) packages, both with operating temperature range of 230°C to 170°C. The NJ8820MA is available only in Ceramic DIL package with operating temperature range of 240°C to 185°C.
PDA PDB LD FIN VSS VDD OSC IN OSC OUT D0 D1 1 2 3 4 5 20 19 18 17 16 CH RB MC DS2 DS1 DS0 PE ME D3 D2
NJ8820
6 7 8 9 10 15 14 13 12 11
DP20, MP20, DG20
FEATURES
s s s s
Low Power Consumption Direct Interface to ROM or PROM High Performance Sample and Hold Phase Detector >10MHz Input Frequency
Fig.1 Pin connections - top view
ABSOLUTE MAXIMUM RATINGS
20·5V to 7V Supply voltage, VDD2VSS Input voltage 7V Open drain outputs, pins 3 and 13 VSS20·3V to VDD10·3V All other pins Storage temperature 265°C to 1150°C (DG package, NJ8820MA) 255°C to 1125°C Storage temperature (DP and MP packages, NJ8820)
ORDERING INFORMATION
NJ8820 BA DP Plastic DIL Package NJ8820 BA MP Miniature Plastic DIL Package NJ8820 MA DG Ceramic DIL Package
MEMORY ENABLE (ME) 13 PROGRAM ENABLE (PE) 14 PULSE DETECT SEQUENCE COUNTER
DATA SELECT OUTPUTS DS0 DS1 DS2 15 16 17 TO INTERNAL LATCHES
RB 19
CH 20
OSC IN OSC OUT
7 8
REFERENCE COUNTER (11BITS)
42
fr
SAMPLE/HOLD PHASE DETECTOR FREQUENCY/ PHASE DETECTOR
1
PDA
LATCH 6 LATCH 7 LATCH 8
2
D0 DATA D1 INPUTS D2 D3
9 10 11 12
PDB
3 VSS
LOCK DETECT (LD)
LATCH 4 LATCH 5
LATCH 1 LATCH 2 LATCH 3
FIN
4
`A' COUNTER (7 BITS)
`M' COUNTER (10 BITS)
fv
VDD VSS
6
CONTROL LOGIC 5
18
MODULUS CONTROL OUTPUT (MC)
Fig.2 Block diagram
NJ8820
ELECTRICAL CHARACTERISTICS AT VDD = 5V
Test conditions unless otherwise stated: VDDVSS=5V ±0·5V. Temperature range NJ8820 BA: 30°C to +70°C; NJ8820 MA: 40°C to +85°C DC Characteristics Characteristic Min. Supply current OUTPUT LEVELS Memory Enable Output (ME) Low level Open drain pull-up voltage Data Select Outputs (DS0-DS2) High level Low level Modulus Control Output (MC) High level Low level Lock Detect Output (LD) Low level Open drain pull-up voltage PDB Output High level Low level 3-state leakage current INPUT LEVELS Data Inputs (D0-D3) High level Low level Program Enable Input (PE) Trigger level Value Typ. 3·5 0·7 Max. 5·5 1·5 mA mA Units Conditions fosc, fFIN = 10MHz fosc, fFIN = 1·0MHz 0 to 5V square wave
0·4 7 4·6 0·4 4·6 0·4 0·4 7 4·6 0·4 60·1
V V V V V V V V V V µA
ISINK = 4mA
ISOURCE = 1mA ISINK = 2mA ISOURCE = 1mA ISINK = 1mA ISINK = 4mA
ISOURCE = 5mA ISINK = 5mA
4·25 0·75 VBIAS 6100mV
V V V
TTL compatible See note 1 VBIAS = self-bias point of PE (nominally VDD/2)
AC Characteristics Characteristic Min. FIN and OSC IN input level Max. operating frequency, fFIN and fosc Propagation delay, clock to MC PE pulse length, tW Data set-up time, tDS Data hold time, tDH Digital phase detector propagation delay Gain programming resistor, RB Hold capacitor, CH Output resistance, PDA Digital phase detector gain Power supply rise time 200 10·6 30 5 1 10 500 5 1 5 0·4 100 50 Value Typ. Max. Units Conditions
mVRMS 10MHz AC-coupled sinewave MHz Input squarewave VDD to VSS, See note 5. See note 2. ns Pulse to VSS or VDD. µs µs ns ns k See note 3. nF k V/Rad 10% to 90%, see note 4. µs
NOTES 1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs. 2. All counters have outputs directly synchronous with their respective clock rising edges. 3. The finite output resistance of the internal voltage follower and `on' resistance of the sample switch driving this pin will add a finite time constant to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs, typically. 4. To ensure correct operation of power-on programming. 5. Operation at up to 15MHz is possible with a full logic swing but is not guaranteed.
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