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Details, datasheet, quote on part number:NJ88C25KA
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Datasheet text preview:
THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
NJ88C25 NJ88C25 IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
DS3280-1.3
NJ88C25
FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE)
The NJ88C25 is a synthesiser circuit fabricated on the GPS CMOS process and is capable of achieving high sideband attenuation and low noise performance. It contains a reference oscillator, 11-bit programmable reference divider, digital and sample-and-hold comparators, 10-bit programmable `M' counter, 7-bit programmable `A' counter, latched and buffered Band 0 and Band 1 outputs and the necessary control and latch circuitry for accepting and latching the input data. Data is presented serially under external control from a suitable microprocessor. Although 30 bits of data are initially required to program all counters, subsequent updating can be abbreviated to 19 bits, when only the `A', `M' and `B' counters require changing. The NJ88C25 is intended to be used in conjunction with a twomodulus prescaler such as the SP8710 series to produce a universal binary coded synthesiser.
PDA PDB FV LD FIN VSS VDD BAND 0 OSC IN 1 2 3 4 18 17 16 15 CH RB MC CAP ENABLE CLOCK DATA BAND 1 OSC OUT
5 NJ88C25 14 6 7 8 9 13 12 11 10
FEATURES s Low Power Consumption
DG18, DP18, MP18
Fig.1 Pin connections - top view
s High Performance Sample and Hold Phase Detector s Serial Input with Fast Update Feature
ORDERING INFORMATION
NJ88C25 KA DG Ceramic DIL Package NJ88C25 KA DP Plastic DIL Package NJ88C25 KA MP Miniature Plastic DIL Package
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VDD2VSS: 20·5V to 7V Input voltage Open drain output, pins 3 and 4: 7V All other pins: VSS20·3V to VDD10·3V Storage temperature: 265°C to 1150°C (DG package) 255°C to 1125°C (DP and MP packages)
RB 17 CAP 15 CH 18
OSC IN OSC OUT
9 10
REFERENCE COUNTER (11BITS)
42
fr
SAMPLE/HOLD PHASE DETECTOR
1
PDA
LATCH 6 LATCH 7 LATCH 8 12 DATA 14 ENABLE 13 `B' REGISTER FREQUENCY/ PHASE DETECTOR 2
`R' REGISTER
fV
PDB
CLOCK
`M' REGISTER
`A' REGISTER
4 VSS 3
LOCK DETECT (LD)
LATCH 6 BAND 0 BAND 1 FIN 8 11 5
LATCH 1 LATCH 2 LATCH 3
LATCH 4 LATCH 5
FV
`M' COUNTER (10 BITS)
`A' COUNTER (7 BITS)
VSS
CONTROL LOGIC VDD VSS 7 6
16
MODULUS CONTROL OUTPUT (MC)
Fig.2 Block diagram
NJ88C25
ELECTRICAL CHARACTERISTICS AT VDD = 5V
Test conditions unless otherwise stated: VDDVSS=2·7V to 5·5V. Temperature range = 30°C to +70°C DC Characteristics Value Characteristic Min. Supply current Typ. 5·5 0·7 3·7 Max. mA mA mA fosc, fFIN = 20MHz fosc, fFIN = 1MHz fosc, fFIN = 10MHz Units Conditions
OUTPUTS Modulus Control (MC), BAND 1 and BAND 2 High level Low level Lock Detect (LD) and FV Low level Open drain pull-up voltage PDB High level Low level 3-state leakage current AC Characteristics
VDD20·4 0·4 0·4 7·0 4·6 0·4 ± 0·1
V V V V V V µA
ISOURCE = 1mA ISINK = 1mA ISINK = 4mA
ISOURCE = 4mA ISINK = 4mA
Value Characteristic Min. FIN and OSC IN input level Max. operating frequency, fFIN and fosc Propagation delay, clock to modulus control MC Programming Inputs Clock high time, tCH Clock low time, tCL Enable set-up time, tES (see note 5) Enable hold time, tEH Data set-up time, tDS Data hold time, tDH Clock rise and fall times Positive threshold Negative threshold Phase Detector Digital phase detector propagation delay Gain programming resistor, RB Hold capacitor, CH Programming capacitor, CAP Output resistance, PDA 200 20 30 0·5 0·5 0·2 0·2 0·2 0·2 0·2 3 50 Typ. Max. mV RMS 10MHz AC-coupled sinewave MHz Input squarewave VDD to VSS, ns See note 2 Units Conditions
tCH
2 500 5 1 1 5
ns k nF nF k
NOTES 1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs. 2. All counters have outputs directly synchronous with their respective clock rising edges. 3. The finite output resistance of the internal voltage follower and `on' resistance of the sample switch driving this pin will add a finite time constant to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs. 4. The inputs to the device should be at logic `0' when power is applied if latch-up conditions are to be avoided. This includes the OSC IN and FIN inputs. 5. Clock to enable set-up time (tES) is variable, dependent on fOSC. It needs to be specified in terms of fOSC, clock high time (tCH) and clock low time (tCL) and must meet the following conditions: 431/fOSC2
µs µs µs µs µs µs µs V V
All timing periods are referenced to the negative transition of the clock waveform. See note 5 TTL compatible, see note 1
See note 3
0 to 5V square wave
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