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Details, datasheet, quote on part number:NWK937
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Datasheet text preview:
NWK937
NWK937
10/100 Fast Ethernet Transceiver to MII Advance Information
Supersedes June 1998 Edition DS4843 - 3.1 Sept 1998
TX_ER TXD3 TXD2 TXD1 TXD0 RX_ER RXD3 RXD2 RXD1 RXD0 DVDD2 DGND2 RX_CLK RX_DV CRS COL
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The NWK937 is compatible with the Auto Negotiation section of IEEE 802.3u and provides all the support needed for the 802.3x Full duplex specification. The NWK937 has multiple operating modes as described in the control section.
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The NWK937 is a single chip CMOS physical layer solution from MII to the magnetics. It is designed for 1 0 B A S E - T and 100BASE-TX Ethernet, based on the IEEE 802.3 specifications.
FEATURES s Integrated 10/100 Mbps Ethernet in a Single Chip Solution s Half duplex and full duplex in both 10BASE-T and 100BASE-TX s IEEE 802.3 compliant MII interface s Link Status Change Interrupt s Extended Register Set s Integrated 10BASE-T Transceivers and Receive / Transmit Filters s Integrated Adaptive Equaliser and Base Line Wander Correction s Full Auto Negotiation Support for 10BASE-T and 100BASE-TX both Half and Full Duplex s Low Dynamic Current s Low Power Mode s Internal Power on Reset s 64 pin QFP Package s Available in 64 Thin PQFP package s Single Magnetics for 10BASE-T and 100BASE-TX Operation for a Single RJ45 Connector
TX_CLK DGND1 TX_EN FDST LNKST SPDST ACTST COLST DVDD1 RXGND3 RXVDD3 PA4 RESET_N RXVDD2 RXGND2 PA3
RXEN DVDD3 MDC MDIO DGND3 RefCLK OSCVDD XTAL1 XTAL2 OSCGND TXGND4 TXVDD4 TXVDD3 TXGND3 TxRef100 TxRef10
RXGND1 RXIP RXIN RXVDD1 RPTR ANEN TXOE TXVDD1 TXON TXOP TXGND1 TXGND2 PA2 PA1 PA0 SUBVDD
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TP64
Fig.1 Pin connections - top view
s Support for Flow Control 802.3x Specification s Integrated 5 LED Driver s Low External Component Count ORDERING INFORMATION NWK937/CG/TP1N
Switch or MAC
NWK937
Isolation Magnetics
RJ45
Fig.2 System block diagram
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NWK937
FUNCTIONAL DESCRIPTION
The NWK937 has three basic operating modes: 10BASET mode, 100BASE-TX mode and LOW-POWER mode. The mo d es are selected by bits 11 and 13 respectively in register 0.The Control block is designed to manage these modes by starting and stopping the two transceivers in a well-controlled manner such that no spurious signals are o u t p u t on either the MII or twisted-pair interfaces. Furthermore, it continuously monitors the behaviour of the transceivers and takes corrective action if a fault is detected.
TX10 Pulse Shaper & Filter
The Pulse Shaper & Filter employs a digital finite impulse response filter (FIR) to pre-compensate for line distortion and to remove high frequency components in accordance with the 802.3 Standard. The Pulse Shaper & Filter is disabled when not in 10BASE-T mode.
TX10 Latency
When connected to appropriate magnetics the latency through the TX10 path is less than 2BT (200ns) for data transmissions. This timing is measured from the falling edge of TX_CLK to the output of the transmit magnetics. The TX10 path will not transmit the first two Manchester encoded bits of a data transmission, as permitted by the 802.3 Standard.
25MHZ REFERENCE CLOCK
T h e NWK937 requires a 25MHz +/-100ppm timing reference for 802.3 compatible operation. This may be supplied either from the integrated oscillator or from an external source. When the integrated oscillator is used, a suitable crystal must be connected across the XTAL1 & XTAL2 pins (see "External Components"). When an external source is used, it must be input to the REFCLK pin and XTAL1 must be tied high. XTAL2 must be unconnected.
RX10 Filter & RX10 Signal Detect
These blocks work in unison to remove noise and to block signals that do not achieve the voltage levels specified in 802.3. Signals that do not achieve the required level are not sampled in the Clock Recovery block and are not passed to the outputs.
10BASE-T OPERATION 10Mb/s Data Transfer on the MII
10Mb/s data is transferred across the MII with clock speeds of 2.5MHz. The MAC outputs data to the NWK937 via the MII interface, on the TXD[3:0] bus. This data is synchronised to the rising edge of TX_CLK. To indicate that there is valid data for transmission on the MII, the MAC sets the TX_EN signal active. This forces the NWK937 device to take in the data on the TXD[3:0] bus. This is serialised and directly encoded as Manchester data, before being output on the TXOP/TXON differential output for transmission through 1:1 magnetics and onto the twisted-pair. The Pulse Shaper & Filter employs a digital finite impulse response filter (FIR) to pre-compensate for line distortion and to remove high frequency components in accordance with the 802.3 Standard. The transmit current is governed by the current through the TXREF10 pin, which must be g r o u n d e d through a resistor as described in "External Components".
RX10 Latency
When connected to appropriate magnetics the latency through the RX10 path is less than 6BT (600ns). This timing is measured from the input of the receive magnetics to the falling edge of RX_CLK. The RX10 path may ignore up to three Manchester encoded bits at the start of data reception (802.3 allows up to 5 bits).
100BASE-TX OPERATION 100Mb/s Data Exchange on the MII Interface
100Mb/s data is transferred across the MII using a 25MHz clock signal. The MAC outputs data to the NWK937 via the MII interface, on the TXD[3:0] bus. This data is synchronised to the rising edge of TX_CLK. To indicate that there is valid data for transmission on the MII, the MAC sets the TX_EN signal active. This forces the NWK937 device to take in the data on the TXD[3:0] bus and replace the first octet of the MAC preamble with Start-of-Stream Delimiter (SSD) symbols to indicate the start of the Physical Layer Stream. When the data transfer across the MII is complete, the MAC deasserts the TX_EN signal and the NWK937 adds End-of-Stream Delimiters (ESD) symbols onto the end of the data stream. The complete data stream (the Physical Layer Stream) is encoded from 4 bits into 5 bits, scrambled, converted to MLT3 and driven to the TXOP and TXON pin differentially. The TX100 path is disabled when not in 100BASE-TX mode and, with the exception of the RX100 Signal Detect, the RX100 Receive Path is disabled when not in 100BASE-TX mode.
RX10 Clock Recovery
The NWK937 employs a digital delay line controlled by the 100MHz Synthesizer DLL to derive a sampling clock from the incoming signal. The recovered clock runs at twice the data rate (nominally 20MHz). When a signal is received from the Signal Detect block, it is used to strobe Link Pulses and Manchester encoded serial data. The Manchester data stream will be decoded into a 4-bit parallel data bus, RXD[3:0]. The RXD bus is clocked out on RX_CLK rising. The NWK937 must detect the first 4 bits of pre-amble before RX_DV is set high. With RX_DV is high, any Manchester coding violation will set RX_ER high. RX_DV is reset by a continuous sequence of zeroes, or by the endof-packet IDLE terminator (11 11 00 00). Whilst RX_DV is low, the data on the RXD bus is always zero.
100MHz Synthesizer
This synthesizer employs a delay-locked loop (DLL) to g e n e r a t e a 100MHz timing reference from the 25MHz reference clock. This 100MHz reference is used by the 10BASE-T transmit and receive functions and is divided by 5 to provide a 20MHz data strobe. The 20MHz clock is used to derive the 2.5 MHz TX_CLK in 10BASE-T mode. The synthesizer is disabled when not in 10BASE-T mode.
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NWK937
125MHz Synthesizer
This synthesizer employs a phase-locked loop (PLL) to generate a 125MHz timing reference from the 25MHz reference clock. This 125MHz reference is used by the 100BASE-TX transmit function and is divided by 5 to provide a 25MHz data strobe on TX_CLK. TX_CLK is frequency and phase locked to the 25MHz reference with a small phase offset. The synthesizer is disabled when not in 100BASE-TX mode. (nominally 125MHz) and is used to clock the MLT3 decoder and the Serial to Parallel converter (SIPO). The recovered clock is divided by 5 to generate the receive clock (RX_CLK) which is used to strobe received data across the MII interface. When no signal is detected in 100BASE-TX mode, the PLL is locked to the reference clock and runs at 125MHz. This e n s u r e s that RX_CLK runs continuously at 25MHz in 100BASE-TX mode. When a signal is present, the Clock Recovery PLL remains locked to the reference until the equalizer has adjusted, then it requires up to 1ms to phase lock to the incoming signal. No data is passed to the MII interface until lock is established.
TX100 PISO, Encoder and Scrambler
The TX100 PISO, Encoder and scrambler loads data from the MII on the rising edge of TX_CLK, and converts them to serial MLT3 for outputting to the TX100 Driver. The TXD[3] bit is output first. The PISO & Encoder do not operate until the 125MHz Synthesizer is locked to the 25MHz reference. This avoids transmission of spurious signals onto the twisted-pair.
RX100 SIPO, Decoder and Descrambler
The RX100 SIPO, Decoder and descrambler convert the received signal from serial MLT3 to 4-bit wide parallel receive data on the MII. This appears on the RXD[3:0] bus which is clocked out on the rising edge of RX_CLK. When a frame starts the NWK937 decodes the SSD symbols and then asserts the RX_DV signal, in order to inform the MAC that valid data is available. When the NWK937 detects the ESD, it deasserts the RX_DV signal.
TX100 Driver
The TX100 Driver outputs the differential signal onto the TXOP and TXON pins. It operates with 1:1 magnetics to provide impedance matching and amplification of the signal in accordance with the 802.3 specifications. The transmit current is governed by the current through the TXREF100 pin, which must be grounded through a resistor as described in "External Components". The TX100 driver is disabled in 10BASE-T mode and in loop back mode.If no data is being transmitted from the MAC, the NWK937 outputs idle symbols of 11111 (suitably scrambled).
RX100 Latency
The latency from the first bit of the "J" symbol on the cable to CRS assertion is between 11 and 15BT. The latency from the first bit of the "T" symbol on the cable to CRS de-assertion is between 19 and 23BT.
100Mb/s Transmit Errors
If the NWK937 detects that the TX_ER signal has gone active whilst the TX_EN signal is active, then it will propagate the detected error onto the cable by transmitting the symbol "00100" . Figure 3 shows the meaning of the different states of TX_EN and TX_ER. TX_ER is sampled inside the NWK937 on the rising edge of TX_CLK.
TX100 Latency
The transmit latency from the first TX_CLK rising when TX_EN is high to the first bit of the "J" symbol on the cable is 8BT.
RX100 Equalizer & Base-line Wander Correction
T h e RX100 Equalizer compensates for the signal attenuation and distortion resulting from transmission down t h e cable and through the isolation transformers. The Equalizer is self-adjusting and is designed to restore signals received from up to 10dB cable attenuation (at 16MHz). When the Equalizer is active it adjusts to the incoming signal within 1ms. Thereafter, the Equalizer will continuously adjust to small variations in signal level without corrupting the received data. T h e 100BASE-TX MLT3 code contains significant low f r e q u e n c y components which are not passed through the isolation transformers and cannot be restored by an adaptive e q u a l i z e r . This leads to a phenomenon known as basel i n e wander which will cause an unacceptable increase in error rate if not corrected. The NWK937 employs a quantized f e e d b a c k technique to restore the low frequency c o m p o n e n t s and thus maintain a very low error rate even w h e n receiving signals such as the "killer packet" d e s c r i b e d in the TP_PMD spec.
TX_EN TX_ER 0 1 1 X 0 1
TXD [3:0] ignored
Indication Normal inter frame data
0000 through 1111 Normal data transmission 0000 through 1111 Transmit error propagation
Fig 3. 100Mb/s transmit error states
100Mb/s Receive Errors
When there is no data on the cable, the receiver will see only the idle code of scrambled 1's. If a non idle symbol is detected, the receiver looks for the SSD so that it can align the incoming message for decoding. If any 2 non consecutive zeros are detected within 10 bits, but are not the SSD symbols a false carrier indication is signalled to the MII by asserting RX_ER and setting RXD[3:0] to 1110 whilst keeping RX_DV inactive. The remainder of the message is ignored until 10 bits of 1's are detected. If any data is decoded after a SSD which is neither a valid data code nor an ESD, then an error is flagged by setting RX_ER active whilst the RX_DV signal is active. This also happens if 2 idle codes are detected before a
RX100 Clock Recovery
The RX100 Clock Recovery circuit uses a Phase-Locked Loop (PLL) to derive a sampling clock from the incoming signal. The recovered clock runs at the symbol bit rate rate
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