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Details, datasheet, quote on part number:NWK939
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Datasheet text preview:
NWK939
NWK939
10/100 Base-TX Symbol Transeiver Advance Information
DS4733 - 2.2 January 1998
The NWK939 is a CMOS Fast Ethernet Transceiver with integrated clock and data recovery for combined 10BASE-T and 100BASE-TX applications. The device connects through a 5 bit symbol interface directly with the NWK960 and similar controllers that incorporate the PCS function such as the DEC21143. The NWK939 incorporates on-chip filtering and pulse shaping to allow use of common 1:1 magnetics (isolation transformers) for both 10 Mb/s and 100 Mb/s modes.
FEATURES s 10BASE-T and 100BASE-TX switchable s IEEE-802.3 compatible s Connects with NWK960 for complete 10/100 NIC solution s Single 1:1 magnetics module for both 10BASE-T and 100BASE-TX s Industry standard Symbol Interface s Supports half and full-duplex operation s Low latency s Integrated diagnostic loopback s Low power mode s Operates with crystal oscillator or external clock source s Integrated filters and pulse shaping s Quantized Feedback circuitry to correct Base Line Wander s Integrated clock recovery and clock synthesis s Integrated adaptive equalizer s Full support for auto-negotiation signalling s Internal loop filter components s Low external component count
RDAT3 RDAT4 RXC SDT100 ASDT RXGND3 RXVDD3 LPWR_N RESET_N RXVDD2 RXGND2 TXOE RDOE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 RDAT2 51 RDAT1/SDT10 50 RDAT0/DAT10 49 TXC 48 DIGVDD 47 DIGGND 46 TDAT0 45 TDAT1 44 TDAT2 43 TDAT3 42 TDAT4 41 TP_RDM 40 TP_RDP 39 38 37 36 35 34 33 32 31 30 29 28 27
TP_TDP REFCLK OSCVDD XTAL1 XTAL2 OSCGND TXGND4 TXVDD4 SUBVDD TXVDD3 TXGND3 TXREFF100 TXREF10
Fig.1 Pin connections - top view
s s s s
Low power CMOS technology Single +5V supply 52 Pin PQFP package Also available in Thin PQFP package
ORDERING INFORMATION NWK939C/CG/GH1N NWK939/CG/TP1N thin quad
NWK936 10/100 PCS or NIC Controller (NWK960, DEC21143 or similar) or Repeater Controller (NWK950, MXIC98741 or similar) Symbol Interface Isolation Magnetics
NWK939
RXGND1 RXIP RXIN RXVDD1 N/C N/C TXVDD1 TXON TXOP TXGND1 TXGND2 LBEN N10/100
GP52 TP52
RJ-45
Fig.2 System block diagram
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NWK939
OVERVIEW
T h e NWK939 is a mixed-signal CMOS 10/100Mb/s transceiver which integrates all of the signal processing components of the dual speed Ethernet Physical Layer. It is designed for compliance with IEEE802.3 Standards and directly interfaces to a variety of Network Interface Card and Repeater controller devices through the industry standard symbol interface. The NWK939 employs robust design techniques to provide a very low bit-error rate and automatic recovery from fault conditions. Compliance to Standards The NWK939 is designed for compliance with the IEEE 802.3 Standard, Clauses 14, 24 & 25, henceforth referred to as 802.3. The 802.3 PMD sub-layer for 100BASE-TX is derived from the FDDI TP-PMD Standard, henceforth referred to as TP-PMD. Compatibility With Other Devices For Network Interface Card applications the NWK939 is designed to operate with controllers such as the NWK960 and the DEC21143, connecting via the symbol interface. For 100BASE-TX repeater applications the NWK939 is designed to operate with controllers such as the NWK950 and MXIC98741, also connecting via the symbol interface.
TX10REF TP_TDP TX10 PULSE SHAPER & FILTER 100MHz SYNTHESIZER LOOPBACK TX10 DRIVER
TP_RDP TP_RDM TXC RXC RDAT[4:0] ASDT RX100 SIPO & DECODER RX100 CLOCK RECOVERY RX100 EQUALIZER & BLW CORRECTION LOOPBACK 125MHz SYNTHESIZER TX100 PISO & ENCODER TX100 DRIVER TX100REF RX10 CLOCK RECOVERY RX10 SIGNAL DETECT RX10 FILTER TXOP TXON RXIP RXIN
SDT100
RX100 SIGNAL DETECT
TDAT[4:0]
POWER ON RESET OSC
CONTROLS
RESET_N
LPWR_N
RDOE
TXOE
REFCLK
Fig.3 NWK939 block diagram
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N10/100
XTAL1
XTAL2
LBEN
NWK939
FUNCTIONAL DESCRIPTION
The NWK939 has three operating modes: 10BASE-T mode, 100BASE-TX mode and LOW-POWER mode. The modes are selected by the N10/100 and LPWR_N pins.The Control block is designed to manage these modes by starting and stopping the two transceivers in a well-controlled manner such that no spurious signals are output on either the symbol or twisted-pair interfaces. Furthermore, it continuously monitors the behaviour of the transceivers and takes corrective action if a fault is detected. TX10 Latency When connected to appropriate magnetics the latency through the TX10 path is less than 1BT (100ns) for data transmissions. This timing is measured from the falling edge of TXC to the output of the transmit magnetics. The TX10 path will not transmit the first two Manchester encoded bits of a data transmission, as permitted by the 802.3 Standard. RX10 Filter & RX10 Signal Detect These blocks work in unison to remove noise and to block signals that do not achieve the voltage levels specified in 802.3. Signals that do not achieve the required level are not sampled in the Clock Recovery block and are not passed to the DAT10/ SDT10 and TP_RDP/TP_RDM outputs. RX10 Clock Recovery The RX10 Clock Recovery employs a digital delay line controlled by the 100MHz Synthesizer DLL to derive a sampling clock from the incoming signal. The recovered clock runs at twice the data rate (nominally 20MHz). When a signal is received from the Signal Detect block, SDT10 is asserted and falling RXC is used to strobe Link Pulses and Manchester encoded serial data out on DAT10 and TP_RDP/TP_RDM. When no signal is being received, SDT10 is deasserted, RXC is driven from the 20MHz transmit clock, DAT10 is held low and TP_RDP/TP_RDM is driven to the zero state (see "DC Electrical Characteristics"). RX10 Latency When connected to appropriate magnetics the latency through the RX10 path is less than 1BT (100ns). This timing is measured from the input of the receive magnetics to the falling edge of RXC. The RX10 path may ignore up to three Manchester encoded bits at the start of data reception (802.3 allows up to 5 bits) and the first bit forwarded to TP_RDP/TP_RDM may have timing violations (802.3 allows 1 bit).
25MHz REFERENCE CLOCK
The NWK939 requires a 25MHz +/-100ppm timing reference for 802.3 compliant operation. This may be supplied either from the integrated oscillator or from an external source. When the integrated oscillator is used, a suitable crystal must be connected across the XTAL1 & XTAL2 pins (see "External Components"). When an external source is used, it must be input to the REFCLK pin and XTAL1 must be tied high. XTAL2 must be unconnected.
10BASE-T OPERATION
In 10BASE-T mode Manchester encoded serial data is loaded from the TP_TDP input, processed through the TX10 Path and output on the TXOP/TXON differential output for transmission through 1:1 magnetics and onto the twisted-pair. The incoming signal received from the magnetics into the RXIP/RXIN differential input is processed through the RX10 Path. Received data is output serially on 2 interfaces. The DAT10 & SDT10 signals form a Mitel Semiconductor-specific interface for connection to the NWK936 PCS device. For NIC controllers that have in-built 10BASE-T receivers, the received signal is also provided on the TP_RDP/TP_RDM differential output. The TX10 & RX10 paths are disabled when the device is not in 10BASE-T mode. 100MHz Synthesizer This synthesizer employs a delay-locked loop (DLL) to generate a 100MHz timing reference from the 25MHz reference clock. This 100MHz reference is used by the 10BASE-T transmit and receive functions and is divided by 5 to provide a 20MHz data strobe on TXC. The synthesizer is disabled when not in 10BASE-T mode. TX10 Pulse Shaper & Filter This block loads Link Pulses and Manchester encoded serial data from the TP_TDP input on the falling edge of TXC. This input may be connected directly to the TP_TDP output of the DEC21143 and similar NIC controllers. The Pulse Shaper & Filter employs a digital finite impulse response filter (FIR) to precompensate for line distortion and to remove high frequency components in accordance with the 802.3 Standard. The Pulse Shaper & Filter is disabled when not in 10BASE-T mode. TX10 Driver The TX10 Driver operates with 1:1 magnetics to provide impedance matching and amplification of the signal in accordance with the 802.3 specifications. The transmit current is governed by the current through the TXREF10 pin, which must be grounded through a resistor as described in "External Components".
100BASE-TX OPERATION
In 100BASE-TX mode 5-bit NRZ symbols are loaded from the TDAT bus, processed through the TX100 Path and output on the TXOP/TXON differential output for transmission through the 1:1 magnetics and onto the twisted-pair. The incoming signal received from the magnetics into the RXIP/RXIN differential input is processed through the RX100 Path and output in 5-bit parallel NRZ form on the RDAT bus. The TX100 path is disabled when not in 100BASE-TX mode and, with the exception of the RX100 Signal Detect, the RX100 Receive Path is disabled when not in 100BASE-TX mode. 125MHz Synthesizer This synthesizer employs a phase-locked loop (PLL) to generate a 125MHz timing reference from the 25MHz reference clock. This 125MHz reference is used by the 100BASE-TX transmit function and is divided by 5 to provide a 25MHz data strobe on TXC. TXC is frequency and phase locked to the 25MHz reference with a small phase offset. The synthesizer is disabled when not in 100BASE-TX mode.
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