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Details, datasheet, quote on part number:P1480
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Datasheet text preview:
P1480 LAN CAM
P1480
LAN CAM 1kx64-Bit CMOS Preliminary Information
Supersedes February 1992 edition - version 1 DS3112 - 2.0 September 1995
The P1480 LAN CAM is a 1K X 64-bit fixed-width CMOS C o n t e n t - a d d r e s s a b l e Memory (CAM) aimed at address filtering applications in Local-area Network (LAN) bridges and routers. The architecture of the LAN CAM allows a network station list of any length to be searched in a single memory transaction. This device is also well-suited for other applications that require high-speed data searching such as optical and magnetic disk caches and data base accelerators. Although the internal data path of the P1480 is 64-bits wide, the external interface is multiplexed four ways to allow communication with the device over a 16-bit bus. Vertical cascading and system flag generation require no external logic. The LAN CAM is synchronously controlled by four wires in much the same way as standard memories are controlled. A powerful instruction set increases the control flexibility and minimizes software overhead in typical systems. A data translation facility converts between IEEE 802.3 (CSMA/CD) and 802.5 (Token Ring) address formats on command. Both random access and associative operations are supported by this device. Flexible bit- and word-masking facilities enhance the associative operations. These and other features make the P1480 a powerful, yet easy to use, associative memory which drastically reduces data search delays.
NC 7 8 9 10 11 12 13 14 15 16 17
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 VCC GND DQ6 DQ7 DQ8 DQ9 DQ10 DQ11
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
/EC /CM /FI /FF /MI /MF GND VCC /E /W DQ15 DQ14 DQ13 DQ12
PDIP
22 21 20 19 18 17 16 15
MU9C1480 LANCAM 44-PIN PLDCC PINOUTS
DQ3 5 DQ2 DQ1 DQ0 /CM /EC /FF NC 6 NC NC /FI
DP28
4
3
2
1
44
43
42
41
40
39 38 37 36 NC /MI /MF GND NC VCC VCC NC /E /W NC
FEATURES I 1 K X 64-bit CMOS Content-addressable M e m o r y (CAM) I 6 4 - b i t internal data path multiplexed four ways o v e r a 16-bit I/O interface I S i m p l e four-wire synchronous control directly u s a b l e in conventional memory subsystems I E x t e n s i v e instruction set adds control flexibility M e m o r y Array width can be configured as a m i x t u r e of CAM and RAM on 16-bit boundaries I M e m o r y operations allow random access, a s s o c i a t i v e access, and write-at-next-freea d d r e s s cycles I V e r t i c a l cascading and system flag generation r e q u i r e no external logic I T w o Mask registers allow masking of individual b i t s for both writing and comparing I P r i o r i t y encoder returns highest-priority match address I D e v i c e gives status information after each operation I T w o validity bits per location provide a word m a s k i n g facility and valid or empty information
DQ4 DQ5 NC VCC NC GND GND DQ6 DQ7 NC
PLDCC
35 34 33 32 31 30 29
Fig.1 Pin connections (top view)
I P r o g r a m m a b l e data translation facility converts b e t w e e n IEEE 802.3 and 802.5 formats I M a n u f a c t u r e d in CMOS technology with TTLc o m p a t i b l e inputs and outputs I P a c k a g e d in industry-standard 28-pin PDIP and 4 4 - p i n PLCC packages
18 NC
19 DQ8
20 DQ9
21 DQ10
22 DQ11
23 NC
24 DQ12
25 DQ13
26 DQ14
27 DQ15
28 NC
HP44
1
P1480 LAN CAM
ORDERING INFORMATION
PART NUMBER P1480-12CGDPAS P1480-12CGHPAS P1480-15CGDPAS P1480-15CGHPAS CYCLE TIME 120ns 120ns 150ns 150ns PACKAGE 28-PIN PDIP 44-PIN PLCC 28-PIN PDIP 44-PIN PLCC TEMPERATURE RANGE 0 - 7 0°C 0 - 7 0°C 0-70°C 0-70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Voltage on all Other Pins Temperature Under Bias Storage Temperature 0.5 to 7.0 Volts 0.5 to VCC+0.5 Volts (-2.0 Volts for 10 ns, measured at the 50% point) 40 °C to +85°C 55 °C to +125°C
DC Output Current 20 mA (per Output, one at a time, one second duration) Notes 1. Stresses exceeding those listed under Absolute Maximum Ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied. 2. All voltages are referenced to GND.
OPERATING CONDITIONS
Symbol VCC VIH VIL TA Parameter Operating Supply Voltage Input Voltage Logic "1" Input Voltage Logic "0" Ambient Operating Temperature Min 4.5 2.0 -0.5 0 Typ 5.0 Max 5.5 VCC +0.5 0.8 70 Units Volts Volts Volts °C see notes 2 and 3 below Still Air Conditions
Notes 1. All voltages referenced to GND at the device pin. 2. -1.0V for a duration of 10ns measured at 50% amplitude for Input-only lines (see Fig.9). 3. Common I/O lines are clamped so that signal transients cannot fall below -0.5V.
ELECTRICAL CHARACTERISTICS
Symbol ICC VOH VOL IIZ IOZ Parameter Average Power Supply Current Output Voltage Logic "1" Output Voltage Logic "0" Input Leakage Current Output Leakage Current -2 -10 2.4 0.4 2 10 Min Max 200 Units mA Volts Volts µA µA IOH = -2.0 mA IOL = 4.0 mA VSS VIN VCC VSS VIN VCC; DQn = High Impedance Conditions
CAPACITANCE
Symbol
C
Parameter Input Capacitance Output Capacitance
Max 6 7
Units pF pF
Conditions f=1MHz, VIN=0 V. f=1MHz, VIN=0 V.
IN
C
OUT
2
P1480 LAN CAM
AC TEST CONDITIONS
Input Signal Transitions Input Signal Rise Time Input Signal Fall Time Input Timing Reference Level Output Timing Reference Level 0.0 to 3.0 volts < 3 ns < 3 ns 1.5 volts 0.8 to 2.4 volts
PIN DESCRIPTIONS
DQ0-DQ15 (Data Bus, Common I/O, TTL) The DQ0-DQ15 lines convey data, commands and status to and from the P1480. The direction and nature of the information that flows to or from the device is controlled by the states of /CM and /W. /E (Chip Enable, Input, TTL) The /E input, the main clock control, enables the LAN CAM while LOW, latches the control signals /W, /CM, /EC on its falling edge and releases them on the rising edge, and clocks the Destination or Source Segment counter on its rising edge. /W (Write Enable, Input, TTL) The /W input selects the direction of data flow during a memory cycle. /W LOW selects a Write cycle, and /W HIGH selects a Read cycle. /CM (Data/Command Select, Input, TTL) The /CM input selects whether the inputs on the DQ0D Q 1 5 lines are data or commands. /CM LOW selects Command cycles and /CM HIGH Data cycles. /EC (Enable Comparison, Input, TTL) The /EC input enables the /MF output to show the results of a comparison. If /EC is LOW at the falling edge of /E in a given cycle, the /MF output is enabled. Otherwise, the /MF output is held HIGH. /MF (Match Flag, Output, TTL) The /MF output goes LOW when a valid match occurs during a Comparison cycle if the /EC line was latched LOW by the falling edge of /E at the start of the cycle. /MI (Match Input, Input, TTL) The /MI input is used in vertically cascaded systems to prioritize devices. In a daisy-chained system, the /MF output of one device is connected to the /MI input of the next lowerpriority device in the chain. /FF (Full Flag, Output, TTL) The /FF output indicates that all the memory locations within the device contain valid contents. /FF LOW indicates the Full condition. /FI (Full Input, Input, TTL) The /FI input is used in vertically cascaded systems to generate CAM Memory System Full indication. In a daisychained system, the /FF output of one device is connected to the /FI input of the next-lower priority device in the chain. VCC, GND (Positive Power Supply and Ground) These pins are the main power supply connections to the P1480. VCC must be held at +5V + 10% relative to the GND pin, which is at 0V (system reference potential), for correct operation of the device.
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