|
Details, datasheet, quote on part number:P2800
| |
Datasheet text preview:
COMMERCIAL-IN-CONFIDENCE
P2800 FEBRUARY 1996
PRELIMINARY INFORMATION
DS4468-1.0
P2800
2K x 64BIT MULTI-PORT CONTENT ADDRESSABLE MEMORY
The P2800 2K x 64bit Multi-port Content Addressable Memory (CAM) is designed for address filtering, routing and translation applications in Ethernet, Token Ring, SMDS and ATM systems where high speed operation is necessary. The P2800 will operate up to and beyond the OC-12 data rate of 622MBits s-1. The architecture of the P2800 makes high-speed operation possible through pipelining and interleaving.
208
FEATURES I 2K x 64bit Content Addressable Memory I 50ns Compare cycle time I 15ns Register Read/Write cycle time I Configurable into areas of CAM and RAM on 16-bit boundaries I One Parallel Port with full 64bit-wide I/O interface configurable for 16-, 32- or 64-bit operation I Two Serial Ports configurable for 1-, 4- or 8-bit operation I Synchronization between Parallel and Serial Ports I Direct hardware control through Control Bus I Two 64-bit Comparand Registers I Four 64-bit Mask Registers I Two Match Address Registers I Two Match Data Registers I Configuration Register I Next Free Address Register I Priority Encoder to resolve multiple matches I Data validity control per location
SA0-7 SB0-7 CLKA CLKB Temp. Register A Temp. Register B Serial Count A Serial Count B Next Free Addr. Register Configuration Register Highest Priority Addr. Reg. 0 Highest Priority Addr. Reg. 1 M U X
208-Pin PQFP
208 PQFP
Fig.1 Pin connections - top view
I I I I I I I
Support for list entry aging Simple Vertical cascading using daisy chain scheme Support for 802.3 to/from 802.5 mapping on all ports High-speed pipelined and interleaved operation 5 Volt I/O operation CMOS Technology Packaged in a 208-pin flatpack
/MF0 /MI0 /MF1 /MI1 /MMF0 /MMI0 /MMF1 /MMI1 /SMO /SM1 /FF /FI
Comparand Register A Comparand Register B Mask Register 0 Mask Register 1 Mask Register 2 Mask Register 3 Highest Priority Data Reg. 0 Highest Priority Data Reg. 1 Match Full Logic
DQ0-63 /E /W /CS /RSTA /RSTB /ZCA /ZCB /ALE /MAE /LPD /RST MAS0-1 CT0-11 FS0-1 A0-10
Control
A D D R E S S D E C O D E R
CAM Array 2K x 64
A G E I N G B I T S
V A L I D T Y B I T S
P R I O R I T Y E N C O D E R
AO0-10
A0-2 V0-2
Fig.2 System block diagram
1
COMMERCIAL-IN-CONFIDENCE
P2800
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS Supply voltageVCC Supply voltageVdd DC input voltage DC output voltage DC input current DC output current Temperature under bias Storage temperature OPERATING CONDITIONS Symbol VCC Vdd VIH VIL TA Characteristic Operating voltage (periphery) Operating voltage (core) Input voltage logic "1" Input voltage logic "0" Ambient operating temperature Value Min. 4.50 3.00 2.0 0.50 0 Max. 5.50 3.60 VCC+0.5 0.8 70 Units volts volts volts volts °C still air Conditions 0.5 to 7.0 volts 0.5 to 4.6 volts 0.5 to Vdd +0.5volts 0.5 to Vdd +0.5volts +/20mA +/20mA -40°C to +85°C -55°C to +125°C
ELECTRICAL CHARACTERISTICS Symbol ICC ICC(SB) Idd Idd(SB) VOH VOL IIZ IOZ Characteristic Power supply current periphery Operating voltage (core) Power supply current periphery Operating voltage (core) Output voltage logic "1" OUTput voltage logic "0" Input leakage current Output leakage current Value Min. 2.4 TBD TBD Max. TBD TBD TBD TBD 0.4 TBD TBD Units mA mA mA mA volts volts µA µA Conditions tELEL1=tELEL1(min) /E = HIGH tELEL1=tELEL1(min) /E = HIGH IOH = TBD, VCC=VCC(min) IOH = TBD, VCC=VCC(max) VSS<= Vin<=VCC VSS<= Vin<=VCC
CAPACITANCE Symbol Cin Cout Characteristic Input capacitance Output capacitance Value Min. Max. 6.00 7.00 Units pF pF Conditions f=1MHz, Vin=0V f=1MHz, Vin=0V
AC TEST CONDITIONS Input signal transactions Input signal rise times Input signal fall times Input timing reference Output timing reference 0.0 to 3.0 volts <3ns <3ns 1.5 volts 0.8 to 2.4 volts
2
COMMERCIAL-IN-CONFIDENCE
P2800
FUNCTIONAL DESCRIPTION
CAM Array The CAM Array contains 2K locations that are 64 bits wide. Each location also has two validity bits to indicate Empty, Valid, Temporarily Invalid and Random Access. Three further bits are included to hold age information for the contents of a location. The CAM Array can be configured into an area of CAM and an area of RAM across the width of the array on 16-bit boundaries. The CAM section holds associative data while the RAM section holds associated data. Associated data can be accessed as a function of a match in the associated data. Parallel Port The Parallel Port is 64 bits wide and provides full bandwidth access into the CAM Array. For architectures that use microprocessors or state machines with narrower data buses, the Parallel Port can be alternatively configured as 16 bits or 32 bits wide; under these circumstances, data is multiplexed on the lower-order bits of the parallel port. Data is read from and written to the CAM Array and the Register Set via the Parallel Port. Serial Ports The Serial Ports operate independently, and can be configured to receive data 1 bit, 4 bits or 8 bits per clock cycle. Data from each Serial Port is assembled in a temporary register ready for transfer into either of the two Comparand Registers. The amount of data to be assembled from each Serial Port is loaded into a Serial Port Counter which sets a flag when the preset number clock cycles have been received. Port Synchronization The Parallel and Serial Ports are synchronized through a handshaking scheme. When the preset count value has been reached by one of the Serial Ports, the flag is set which indicates to the local processor that a value has been assembled and is ready for use. The local processor now transfers that data to one of the Comparand Registers ready for comparison.While the Serial Port flag remains set, that Serial Port cannot clock in more data. When the local processor has dealt with the data, it resets the flag and the Serial Port can resume clocking. Therefore, the local processor arbitrates between the asynchronous operation of the Parallel and Serial Ports. Register Set The Register Set comprises two Comparand Registers, four Mask Registers, two Match Address Registers, two Match Data Registers, a Configuration Register, and a Next Free Address Register. The Comparand Registers hold the values for comparison. The comparison is masked by a selected Mask Register. Only bits in the Comparand Register that correspond with bits set LOW in the selected Mask Register are compared, other bits are ignored. Results of comparison are read from the corresponding Match Address Register or Match Data Register. The Match Data Registers provide access to the associated data of the highest-priority matching location. The Next Free Address Register holds the address of the next free location in the device. This information is used for `associative' write cycles to the next free location. The Full Flag daisy chain ensures that write at next free address cycles work globally. The Configuration Register sets up persistent operating conditions within the device. Control States Unlike earlier instruction-driven CAM devices, the P2800 is controlled through the hardware Control Bus, leading to singlecycle operation. This approach provides a substantial increase in operating speed. Control states are input to the P2800 on the Control Bus. These control states divide into four classifications: Read/Write Register, Read/Write Memory, Conditional Write and Compare. The control states give powerful and flexible control over the device. Match Logic Results of comparison are indicated through the Match Flag. There is one Match Flag per Comparand Register. In a vertically cascaded system, each Match Flag is fed from one device into Match Input of the next lower-priority device. This connection forms a match daisy chain, allowing match results to be established on a global basis. Pipelining and Interleaving The combination of Comparand Register, Match Address Register, Match Data Register and Match Flag Input and Output forms a comparison channel. There are two such channels in the P2800. The data is loaded into the Comparand Register associated with one comparison channel, and comparison is initiated; while the comparison is taking place, results from an earlier comparison in the other comparison channel can be read from the Match Address or Data Register associated with that channel. Therefore, a constant stream of data and results can flow through the device, to provide uninterrupted high-speed operation. Vertical Cascading As well as the Match Flag daisy chain, there are daisy chains for both channels of Multiple Match Flags, and a Full Flag daisy chain. All daisy chains operate independently. Aging List entry aging is supported through three extra bits per location. A location can be set to age or not, as data is written to the memory. A fully associative aging algorithm is implemented through the control states.
3
|
|
