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Details, datasheet, quote on part number:VP7615
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Datasheet text preview:
VP7615
Colour Digital Video Camera Decoder IC Advance Information
Supersedes February 1997 edition, DS4602 - 2.4 DS4602 - 3.1 August 1997
The VP7615 iCamHostTM Processor chip can decode the signals from a variety of iVisionTM compatible digital video cameras (such as Silicon Vision's iCamTM) and process them for use in a host computer system. Digital cameras can offer real cost and performance gains in applications which require a digital video input, and iVision technology realises both these benefits. In a typical analog camera the digitised output from the CCD imager is normally encoded into an analog composite video signal which then has to be redigitised at the input to the host system. By employing the iVision approach the output from the camera is maintained as a digital signal, but in a format which allows for a low cost 9wire connection to the host. Eliminating the unnecessary conversion to an analog signal and back again not only saves cost, but also avoids any possible degradation of image quality. Other benefits include direct control of the camera from the host and the ability to power the camera from the host system so saving the cost of a separate power supply. The VP7615 supports two software selectable CamPortTM interface ports, either of which can receive the digital video from an iVisionTM compatible digital video camera. The output is a standard colour digital video signal, similar to standard composite analog-digital decoder chips such as the Philips SAA7110 and SAA7111. All iCamHostTM operating modes are controlled by the host PC via an I2C interface. Hardware I/O controls include output enable and I2C address offset. NOTE: iCamTM, CamPortTM and iCamHostTM are trademarks of Silicon Vision, Inc., Fremont, CA
FEATURES
I Accommodates different camera configurations based on a variety of CCD imager resolutions I Requires only a small, low-cost 9 pin mini-DIN to connect to camera I Receives the image signal from the camera in digital form at a frame rate determined by the host I Decodes all necessary synchronisation and clock signals from the digital data stream I P r o g r a m m a b l e gamma correction curve in RGB colourspace I Programmable colour-separation matrix I Collects image status data within user-defined rectangular gated zone of CCD sensor I Programmable horizontal and vertical aperture correction I Pin-strap selectable output format in 16 bit YUV 4:2:2 or 8 bit CCIR 656 YUV 4:2:2 I Test pattern generator for SMPTE colourbars I Bypass mode to output unprocessed 8 bit CCD pixel samples in the luminance channel I Dual iCamPortTM camera input ports, software selectable I Completely iVisionTM Compatible I Eight general purpose I/O pins for board level configuration control and/or status I Programmable polarity for HSYNC, VSYNC, HACT & VACT control outputs I Chip pinout is backwards compatible with VP7610
ORDERING INFORMATION
VP7615 CG FP1N
VP7615
3 ADDRESS OFFSET I2C CLK,DATA CAMPORT A CAMPORT B 5 SERI AL BUS CONTROLLER 2 5 DEMUX & SYNC RECOVERY C LK1X, C LK2X CTRL
RAM CONTROL CMYG PIXEL SEPARATOR
TWO HORIZONTAL LINE DELAY FIFO RAM
CTRL
COLOUR MATRIX CONVERTER RGB
APERTURE CORRECTION
CTRL
TO SERIAL BUS CONTROLLER MODULE
GAMMA CORRECTION
CTRL
COLOURSPACE CONVERSION CHROMINANCE & LUMINANCE METRICS Y UV
CTRL
CHRO MINANCE SUB-SAMPLING AND FILTERING
CTRL
OUTP UT ENA LE B
OUTPUT FORMATTER
CTRL
BFLAG, FIELD
8 BIT CCIR656/ VSYNC,HSYNC, 16 BIT CCIR601 VACT, HACT
Fig.1 Functional Block Diagram
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VP7615
THEORY OF OPERATION
General Overview The VP7615 iCamHostTM is a fully synchronous real-time p i p e l i n e pixel processor for converting digitized CCD photosite samples into co-sited, colour calibrated, gamma corrected and aperture corrected digital video in an industryconventional format similar to analog video decoders. The VP7615 supports the full iVisionTM Command Set for control of camera head functions such as frame rate, resolution, exposure and colour depth via the CamPortTM Interface. 2 Access to all registers and functions is provided by an I C state machine. Demux and sync recovery The incoming CCD photosite bytes come in a single nibble at a time in a "big-endian" fashion from one of two CamPortTMs. These nibbles are clocked in via a separate pixel clock signal. The formatting signals such as start of active video, end of active video, and start of new frame are all encoded into the nibble stream. The output is an 8 bit byte of CCD sample for each pixel clock, as well as separate horizontal and vertical sync signals. RAM control & 2H line delay FIFO RAM Since the iCamHostTM assumes an interlaced scanning CCD with a CMYG colour mosaic format, the colour content is derived from different locations around where the output video pixel is desired. Specifically, the first line from the CCD contains "red-like" colour content, alternating with the following line containing "blue-like" colour content. The third line is real-time, and the first opportunity to output properly cosited luminance and chrominance as though the colour pixels were superimposed upon themselves, all on the second line. Pixel separator Since the colourspace converter requires the 3 most recent lines of CCD data, this block handles the shuffling of either the 2 red and 1 blue line, or 2 blue and 1 red line of data. Colour matrix converter The input to this converter is derived from the relative sums and differences of the above 3 lines of sample data, and p r o c e s s e s them through a programmable 3x3 matrix multiplier. The output is colour-separated and calibrated RGB samples. Gamma corrector Since CRT monitors have a non-linear RGB intensity r e s p o n s e to input signal, gamma correction must be performed in RGB space as well to prevent cross-coupling errors between luminance and chrominance. This block is a programmable 16 line-segment curve generator to provide not only gamma correction, but any arbitrary contiguous curve of positive slope, with end points at any level to adjust contrast and range. Colourspace converter Since the output of the processor is to be YUV and not RGB, a fixed-coefficient 3x3 matrix converter is used. Chrominance sub-sampling & filtering Spatial sub-sampling and filtering is performed since the output sampling format must be reduced from 4:4:4 to 4:2:2 b e c a u s e most video systems do not require more chrominance data for video camera input. Output formatter Devices taking digital video input such as capture, graphics and compression chips usually require the YUV to be formatted either in CCIR601 16 bit mode (YU then YV) or CCIR656 8 bit mode(U then Y then V then Y). The output mode (8 vs 16 bit) CCIR601 is pin-strap selectable. Additional control register bits may be used to swap the luma and chroma data or to swap the order of U and V data to support the video input requirements of a variety of bus master or graphics chip video interfaces without external glue logic. The polarity of VSYNC, HSYNC, VACT and HACT is also programmable. An output enable input signal may be used when "bussing" the output with other video decoders. Other useful signals such as field and colour flags are also provided. Timing diagrams illustrating the function of the video outputs at different time scales are given in figures 5 to 8. Aperture corrector Since both the luminance and chrominance are derived from spatially spread pixels and the ideal output would be as though all the pixels were superimposed upon one another, a programmable vertical and horizontal aperture correction can be applied to either "soften" or "sharpen" the image. Scene-sensing luminance and chrominance metrics There are no hard-wired closed-loop control circuits in the processor. To achieve great flexibility in control over the behavior of the camera head and processor system, a userdefined region of interest is programmed which provides statistical information about the field of video only within that r e g i o n . Peak luminance, total luminance, total red chrominance and total blue chrominance are provided and updated after each field. Serial bus control To provide read-write control over the registers within the processor, a standard I2C state-machine is provided. Its address may be offset by 3 bits to preclude address conflicts.
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