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Details, datasheet, quote on part number:Z5380SCSI
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Datasheet text preview:
ZI L O G
Z5380 SCSI
PRODUCT SPECIFICATION
Z5380 SCSI
SMALL COMPUTER SYSTEM INTERFACE (SCSI)
FEATURES
s s s s s
Pin Compatible with the Industry Standard 5380 40-Pin DIP or 44-Pin PLCC Package Styles Low-Power CMOS Asynchronous Interface (Supports 1.5 MB/s) Direct SCSI Bus Interface with On-Board 48 mA Drivers
s s s s s
Supports Target and Initiator Roles Arbitration Support DMA or Programmed I/O Data Transfers Supports Normal or Block Mode DMA Memory or I/O Mapped CPU Interface
GENERAL DESCRIPTION
The Z5380 SCSI (Small Computer System Interface) controller is designed to implement the SCSI protocol as defined by the ANSI X3.131-1986 standard, and is fully compatible with the industry standard 5380. It is capable of operating both as a Target and as an Initiator. Special high-current open-drain outputs enable the Z5380 to directly interface to, and drive, the SCSI bus. The Z5380 has the necessary interface hook-ups which allows the system CPU to communicate with it like any other peripheral device. The CPU can read from, or write to, the SCSI registers which are addressed as standard or memorymapped I/Os (Figure 1). The Z5380 increases the system performance by minimizing the CPU intervention in DMA operations which the SCSI controls. The CPU is interrupted by the SCSI when it detects a bus condition that requires attention. It also supports arbitration and reselection. The Z5380 has the proper hand-shake signals to support normal and block mode DMA operations with most DMA controllers available (Figure 2).
Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below:
Connection
Power Ground
Circuit
VCC GND
Device
VDD VSS
PS97SCC0100
PS009101-0201
1
ZI L O G
Z5380 SCSI
GENERAL DESCRIPTION (Continued)
/DB7-/DB0, /DBP
/ACK
/ATN
/BSY
/MSG
I//O
C//D
/REQ
/RST
/SEL
48 mA SCSI Transceivers
/IOR /IOW /CS /RESET A2-A0 D7-D0 CPU BUS Interface
Interface Control Logic
Data Input Register
Data Output Register
DMA Logic
Interrupt Logic
Control Registers
/EOP
READY
DRQ
/DACK
Figure 1. Z5380 Block Diagram
D7-D0 A2-A0 /IOR /IOW /CS /RESET /DACK /EOP DRQ READY IRQ GND
IRQ
/DB7-DB0, /DBP /ACK /ATN /BSY /MSG
Z5380
I//O C//D /REQ /RST /SEL
VDD
Figure 2. Logic Symbol
2
PS009101-0201
PS97SCC0100
ZI L O G
/DB4 /DB5 /DB6 /DB7 N/C
Z5380 SCSI
D0
D1
D2
D3
D4
D0 /DB7 /DB6 /DB5 /DB4 /DB3 /DB2 /DB1 /DB0 /DBP GND /SEL /BSY /ACK /ATN /RST I//O C//D /MSG /REQ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32
D1 D2 D3 D4 D5 D6 D7 A2 A1 VDD A0 /IOW /RESET /EOP /DACK
/DB3 /DB2 /DB1 /DB0 /DBP GND GND /SEL /BSY /ACK /ATN 7 8 9 10 11 12 13 14 15 16
6
5
4
3
2
1 44 43 42 41 40 39 38 37 36 D6 D7 A2 A1 VDD N/C A0 /IOW /RESET /EOP /DACK
D5
Z5380
35 34 33 32 31 30
Z5380
31 30 29 28 27 26 25 24 23 22 21
17 29 18 19 20 21 22 23 24 25 26 27 28
/CS /REQ /RST /MSG DRQ /IOR I//O C//D IRQ N/C RDY
READY /IOR IRQ DRQ /CS
Figure 3b. 44-Pin PLCC Pin Configuration
Figure 3a. 40-Pin DIP Pin Configuration
PIN DESCRIPTION Microprocessor Bus
Figure 3 shows the pins and their respective functions for both the DIP and PLCC. A2-A0 Address Lines (Input). Address lines are used with /CS, /IOR, or /IOW to address all internal registers. /CS Chip Select (Input, Active Low). This signal, in conjunction with /IOR or /IOW, enables the internal register selected by A2-A0, to be read from or written to. /DACK DMA Acknowledge (Input, Active Low). /DACK resets DRQ and selects the data register for input or output data transfers. /DACK is used by DMA controller instead of /CS. DRQ DMA Request (Output, Active High). DRQ indicates that the data register is ready to be read or written. DRQ is asserted only if DMA mode is set in the Command Register. DRQ is cleared by /DACK. D7-D0 Data Lines (Bi-directional, three-state, Active High). Bi-directional microprocessor data bus lines. D0 is the Least Significant Bit of the bus. Data bus lines carry data and commands to and from the SCSI. /EOP End of Process (Input, Active Low). /EOP is used to terminate a DMA transfer. If asserted during a DMA cycle, the current byte will be transferred, but no additional bytes will be requested. /IOR I/O Read (Input, Active Low). /IOR is used in conjunction with /CS and A2-A0 to read an internal register. It also selects the Input Data Register when used with /DACK. /IOW I/O Write (Input, Active Low). /IOW is used in conjunction with /CS and A2-A0 to write an internal register. It also selects the Output Data Register when used with /DACK.
PS97SCC0100
PS009101-0201
3
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