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Details, datasheet, quote on part number:Z8613112SSC
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| Part: | Z8613112SSC |
| Category: | Multimedia => Video => TV Applications => Controllers |
| Description: | Speed = 12 ;; Closed-Captioning = no ;; On-screen Display = no ;; V-Chip = no ;; Time of Day = Yes ;; Selectable I²C = no ;; Voltage = 4.75-5.25V ;; |
| Company: | Zilog, Inc. |
| Datasheet: | Download Z8613112SSC datasheet File size : 1934 kB |
| Request For quote: | Find where to buy Z8613112SSC
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Datasheet text preview:
PRELIMINARY PRODUCT SPECIFICATION
Z86129/130/131
NTSC LINE 21 DECODER
FEATURES
Devices Z86129 Z86130 Speed (MHz) 12 12 Pin Count/ Package Types 18-Pin DIP, SOIC 18-Pin DIP, SOIC Standard Temp. Range 0¡ to +70¡C 0¡ to +70¡C On-Screen Display & Closed Captioning Yes No Automatic Data Extraction V-Chip Yes Yes* Time of Day Yes Yes* Yes
Z86131 12 18-Pin DIP, SOIC 0¡ to +70¡C No No Note: *The Z86130 recovers the line 21 data in both of field1 and field2. It also has V-Chip-specific registers and the output (pin-13)
to control program blocking with minimal communications between the Z86130 and the host processor.
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Complete Stand-Alone Line 21 Decoder for ClosedCaptions and Extended Data Services (XDS). Preprogrammed to Provide Full Compliance with EIA608 Specifications for Extended Data Services. Automatic Extraction and Serial Output of Special XDS Packets such as Time of Day, Local Time Zone, and Program Blocking (V-Chip). Cost-Effective Solution for NTSC Violence Blocking inside Picture-in-Picture (PiP) Windows.
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Minimal Communications and Control Overhead Provides Simple Implementation of Violence Blocking, Closed Captioning, and Auto Clock Set Features. Programmable, Full Screen On-Screen Display (OSD) for Creating OSD or Captions inside a Picture-in-Picture (PiP) Window (Z86129 only). I2C Serial Data and Control Communication User-Programmable Horizontal Display Position for easy OSD Centering and Adjustment (Z86129 only).
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GENERAL DESCRIPTION
The Z86129/130/131 is a stand-alone integrated circuit, capable of processing Vertical Blanking Interval (VBI) data from both fields of the video frame in data conforming to the transmission format defined in the Television Decoder Circuits Act of 1990 and in accordance with the Electronics Industry Association specification 608 (EIA608). The Line 21 data stream can consist of data from several data channels multiplexed together. Field 1 has four data channels: two Captions and two Text. Field 2 has five additional data channels: two
Captions, two Text and Extended Data Services (XDS). XDS data structure is defined in EIA608. The Z86129 can recover and display data transmitted on any of these nine data channels. The Z86130 and Z86131 are derivatives of the Z86129. The Z86130 and Z86131 do not have OSD capability, but are ideally suited for Line 21 data slicer applications.
The Z86129/130/131 can recover and output to a host processor via the I2C serial bus the recovered XDS data packet defined in EIA608 as it is defined in the table above (Z86130 provides the raw Line 21 data, which must be decoded properly for the applications). On-chip XDS filters in Z86129 is fully programmable, enabling recovery of only those XDS data packets selected by the user.The Z86131 is designed especially for extracting XDS time information with proper XDS filter setup for Automatic Clock-Set features in TVs, VCRs, and Set-Top boxes. And the Z86130 is designed especially for V-Chip and Line 21 data recovery. In addition, the Z86129/130 is ideally suited to monitor Line 21 of video displayed in a PiP window for violence blocking purposes. A block diagram of the Z86129/130/131 is illustrated in Figures 1 and 2.
DS007200-TVX0199
1
VIN/
Intro
SMS SEN SCK SDA SDO
Dual Clamp SIG PG Digital II Lock Test Reg
VW
AW
FEW
Status Reg
Command Processor Row Latch 4 10 Address MUX 6 DOT CLK DIV Display RAM ADDR DEC Display 8 Latch FLD SS CTR 4 Output Logic Line & Field Control V/I Ref Line & Fld Decodes BOX BLUE GREEN RED POR CKT 13 Character Generator ADDR Decoder
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GENERAL DESCRIPTION (Continued)
CSYNC DOT CLK
Slice Level
SYNC Slicer
COMP SYNC
CG Lines V Lock CHAR CLK CW O/S MSGR PH1 OSC CHAR CIR
Figure 1. Z86129 Block Diagram
PRELIMINARY
CG Logic PH2 Control I Drive & MUX FR FLD LS SFLD SLS 9 LPF Loop Filter 1 Vss 11 Vss(A) 10 RREF
5
MSYNC
HIN
17 3 2 18 Z86129 only
Addr Bus
2
+5V VDD 13 6 4 15 14 16 12 Sliced Data Data CLK Recovery Data Bus Row Serial Control Port Data Line Buffer Lock Data Slicer
Z86129/130/131 NTSC Line 21 Decoder
Video
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DS007200-TVX0199
ZiLOG
ZiLOG
+5V VDD 13 VIN/ Intro SMS SEN SCK SDA SDO 6 4 15 14 16 1 12 Sliced Data Data CLK Recovery Data Bus VW AW Digital II Lock Test Reg Command Processor Row Latch DOT CLK DOT CLK DIV V Lock CHAR CLK CW O/S MSGR PH1 OSC CHAR CIR Display 8 Latch FLD SS CTR 4 Output Logic Line & Field Control V/I Ref Line & Fld Decodes 3 2 H SEL LPF Loop Filter 9 XOUT 11 Vss(A) 10 RREF POR CKT NC NC 13 Character Generator 4 10 6 Display RAM ADDR DEC ADDR Decoder Address MUX FEW Status Reg Row Serial Control Port I2C SEL Data Line
Dual Clamp SIG PG
8
CSYNC
Slice Level
SYNC Slicer
Figure 2. Z86130/131 Block Diagram
PRELIMINARY
CG Logic PH2 Control I Drive & MUX COMP SYNC CG Lines FR FLD LS SFLD SLS
MSYNC
For Z86129 only
RCLK
5
HIN/XIN
17 18
Addr Bus
DS007200-TVX0199
Buffer Lock Data Slicer
Video
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Z86129/130/131 NTSC Line 21 Decoder
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