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Details, datasheet, quote on part number:Z90110
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Datasheet text preview:
PRELIMINARY
Z90110/120/130 CP95TEL1300
PRELIMINARY CUSTOMERPROCUREMENTSPECIFICATION
Z90110/120/130
40-PINLOW-COSTDIGITAL TELEVISIONCONTROLLER
FEATURES
Part Z90110 Z90120 Z90130
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ROM (KB) 4 6 8
RAM* (Kbyte) 236 236 236
Speed (MHz) 4 4 4
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On-Screen Display (OSD) Logic Circuits One 14-Bit and Three 6-Bit Pulse Width Modulator (PWM) Circuits 24 Input/Output Lines P r o g r a m Memory, Video RAM, and Register File A d d r e s s Spaces Two On-Chip Counter/Timers
*General-Purpose
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40-Pin DIP Package
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4.5V to 5.5V Operating Range 0 °C to +70°C Temperature Range Low-Power Consumption
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GENERAL DESCRIPTION
The Z901XX 40-pin Digital Television Controller is a costeffective member of the Z8 ® single-chip microcontroller f a m i l y . The device provides an ideal performance and reliability solution for consumer and industrial television applications. The Z901XX offers mask-programmed ROM, which enables the Z8 microcontroller to be used in a high-volume p r o d u c t i o n application device embedded with a custom program (customer-supplied program) and combines to provide support for mid-range and low-end TV applications. The device features an 8-bit internal data path controlled by a Z8 microcontroller, On-Screen Display (OSD) logic c i r c u i t s , and Pulse Width Modulators (PWM). On-chip peripherals include two register mapped I/O ports (Ports 2 a n d Port 3), interrupt control logic (one software, two external and three internal interrupts) and a standby mode recovery input port (Port 3, pin P30). The OSD control circuits support six rows by 20 columns of characters. The character color is specified by row. One of the eight rows is assigned to show two kinds of colors for bar type displays such as volume control. The OSD is capable of displaying either low resolution (5x7 dot pattern) or high resolution (11x15 dot pattern) characters. A 14-bit PWM port provides enough voltage resolution for a voltage synthesizer tuning system. Three 6-bit PWM p o r t s are used for controlling audio signal levels, and Three 8-bit PWM ports used to vary picture levels. Three basic address spaces, The Program Memory, Video RAM, and Register File, support a wide range of memory configurations. For applications demanding powerful I/O capabilities, the Z901XX's dedicated input and output lines are grouped i n t o three ports, and are configurable under software control to provide timing, status signals, parallel I/O and an address/data bus for interfacing to external memory. To unburden the program from coping with the real-time problems such as counting/timing and data communication, the Z901XX offers two on-chip counter/timers with a large n u m b e r of user selectable modes.
Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD
VSS
CP95TEL1300 (10/95)
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PRELIMINARY
Z90110/120/130 CP95TEL1300
GENERAL DESCRIPTION (Continued)
XTAL1 XTAL2 /RESET RESET Oscillator WDT Counter Timer Counter Timer P30 P31 P34 P35 P36 P60 P61 P62 P63 P64 P65 AFCIN Port 3/ Interrupt 256 Byte Register File PWM 1 14 -bit PWM 1 6 KByte Program ROM Port 2 Z8 CPU Core P27 P26 P25 P24 P23 P22 P21 P20
Port 6 (Control)
Port 0 A8-15
Port 1 AD0-7
PWM 6 to PWM 8 6-bit
PWM 6 PWM 7 PWM 8
PWM 9 to PWM11
PWM 9 PWM 10 PWM 11
120 Byte Character RAM
On Screen Display
3 KByte Character ROM
OSCIN OSCOUT HSYNC VSYNC VRED VGREEN VBLUE VBLANK
Functional Block Diagram
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PRELIMINARY
Z90110/120/130 CP95TEL1300
PIN CONFIGURATION
PWM1 P35 P36 P34 P31 P30 XTAL1 XTAL2 /RESET P60 GND P61 P62 VCC P63 P64 P65 AFCIN OSCIN OSCOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Z90100 (LDTC)
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
PWM6 PWM7 PWM8 PWM9 PWM10 PWM11 P27 P26 P25 P24 P23 P22 P21 P20 VBLANK VBLUE VGREEN VRED VSYNC HSYNC
40-Pin Mask-ROM Plastic DIP
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