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Details, datasheet, quote on part number:Z90219
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Datasheet text preview:
PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
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Z90219/213/212/211/218
Z8® DIGITAL TELEVISION CONTROLLERS
FEATURES
Device Z90211 Z90218 Z90212 Z90213 Z90219 ROM (KB) 16 (OTP) 8 12 16 32 (ext.) RAM* (Bytes) 237 237 237 237 237 I/O Lines 20 20 20 20 N/A Voltage Range 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V
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On-Chip Infrared (IR) Capture Registers Four Channel 3-bit Analog-to-Digital Converter Twenty General Purpose I/O Pins I2C Serial Communication Port)
Note: OTP and Z9021x products under development
On Screen Display (OSD) Section
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Z8-Based CMOS Microcontroller for Consumer Television, Cable Box, and Satellite Receiver Applications.
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Supports Displays up to 10 rows by 24 Columns with 256 Characters Character Cell Resolution of 14 Pixels by 18 Scan lines Variable Inter-row Spacing from 0-15 Horizontal Scan Lines Foreground and Background Programmable by Character Colors Fully
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42-Pin SDIP Package Z8 Microcontroller Core at 6 MHz Mask ROM sizes Available in 8, 12 and 16 Kbytes Eleven Pulse Width Modulators
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GENERAL DESCRIPTION
The Z9021x Digital Television Controller (DTC) family is Zilog's latest and most powerful Z8-based DTC product offering. These parts feature larger system RAM and ROM options, together with a host of new features including a new color palette system, flexible inter-row spacing, higher character cell resolution, background mesh effect, dedicated I.R. capture registers, on-chip Analog-to-Digital conversion, and a hardware Master mode I2C interface. The familiar Z8 core in combination with these advanced features makes the Z9021x family an ideal choice for low to midrange televisions in both PAL and NTSC markets. The Z9021x family consists of two basic device types; Z9020x and Z9021x. The only difference between the two types is the presence of a hardware I2C serial communication port and half-tone OSD circuitry on the Z9021x family. Of course I2C communication is supported on the Z9020x family in software with the dedication of any two I/O pins to the task. The Z9021x family takes full advantage of the Z8's expanded register file space to offer greater flexibility in On Screen Display creation.
CP96TEL2400
PRELIMINARY
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Z90219/213/212/211 Z8® Digital Television Controllers
Zilog
BLOCK DIAGRAM
XTAL1 XTAL2 /RESET
Oscillator
WDT RESET Counter Timer Counter Timer 3-bit ADC IR Counter Port3
8/12/16K Byte Program ROM Port2 Z8 CPU Core
ADC0 ADC1 ADC2 ADC3 IRIN P30 P31 P34 P35
P20 P21 P22 P23 P24 P25 P26 P27
Register File
Port4
256 Byte PWM 11 (14-bit)
P40 P41 P42 P43 P44 P45 P46 P47
PWM11 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 PWM9 PWM10 P1 P2 P3 P4 P5 P6 P7
PWM 1 to PWM 10 (6-bit)
Character RAM 240 by 11-bit & 10 by 8-bit
I2C Interface
SCLK0 SDATA0 SCLK1 SDATA1 Z9021x ONLY OSDX1 OSDX2 HSync VSync R G B VBlank HLFTN Z9021x ONLY
On Screen Display Output Port
Character ROM
9K by 7-bit
Figure 1. Functional Block Diagram
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PRELIMINARY
CP96TEL2400
Zilog
Z90219/213/212/211 Z8® Digital Television Controllers
PIN IDENTIFICATION
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PWM11/P7 PWM6/P6 PWM5/P5 PWM4/P4 PWM3/P3 PWM2/P2 PWM1/P1 P40 P34/ADC3 P35/ADC2 P41/ADC1 P31/ADC0 AGND P42 P43 P30 P44/PWM7 P45/PWM8 P46/PWM9 P47/PWM10 P20/HLFTN
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Z9021x (Top View)
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P27/SDATA1 P26/SCLK1 P25/SDATA0 P24/SCLK0 P23 P22 IRIN P21 VCC /RESET XTAL2 XTAL1 GND OSDX2 OSDX1 VSYNC HSYNC VBLANK R G B
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CP96TEL2400
PRELIMINARY
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