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Details, datasheet, quote on part number:ZM534
 
 
Part:ZM534
Category:Data Conversion => DAC (Digital to Analog Converters) => <10 bit
Description:Quad 8 Bit DAC Digitrim
Company:ZMD
Datasheet:Download ZM534 datasheet   File size : 111 kB
Request For quote:  Find where to buy ZM534
 



Datasheet text preview:
Preliminary
ZM534
Quad 8 Bit DAC DIGITRIM
Features
Ë 2.7 - 5.5V Power Supply Ë Rail to Rail Input and Output Voltage Range Ë Serial Three-Wire Interface Ë Software Shutdown Ë Simultaneous Update Ë Internal PON with Clear Ë Asynchronous Clear Input Ë Serial Data Output Ë 16 Pin QSOP Package Ë Footprint Compatible to MAXIM's MAX534/533
Applications
Ë Digital Offset and Amplification Adjustment Ë MPU controlled Trimming Operations Ë Usage for General Voltage Trimming Devices
General Description
The DIGITRIM contains quad DAC channels with identical structure. There is an input register followed by a DAC register, resistor string DAC with externally supplied reference and a rail-to-rail voltage output buffer.
Using the three wire interface, data is clocked serial into the 12 bit shift register. Indepent from the four adressing and command bits the contents of shift register is transfered to input register or DAC register when /LDAC goes low ore software command occures. For daisy chaining applications incoming data is outputed delayed 12 or 12 ½ SCLK - clocks at DOUT. After power on or hardware clear all registers are set to zero. The DIGITRIM circuits are manufactured using a 0.8-micron CMOS process.
Functional Diagram
DOUT /CLR /LDAC UPO PDE VDD REFH
CONTRO OUTA IN REG A DAC REG A DAC A
12 Bit SHIFT REG
OUTB IN REG B DAC REG B DAC B
OUTC IN REG C DAC REG C DAC C
OUTD SR CTRL IN REG D DAC REG D DAC D
/CS
DIN
SCLK
DGND
REFL
ZM 534
Figure 1. Block Diagram
1
Preliminary
Pin Configuration
OUTB OUTA REFH UPO PDE /LDAC /CLR DOUT
ZM534
OUTC OUTD REFL VDD DGND DIN SCLK /CS
ZM D ZM 534
Figure2. Pin Configuration
Pin Description
Name OUTB OUTA REFH UPO PDE /LDAC /CLR /DOUT Description DAC B Output DAC A Output Reference Voltage Input (High) User - Programmable Logic Output Power Down Enable Load DAC register with the contents of the input register Clear DAC Input Serial Data Output Name OUTC OUTD REFL VDD GND DIN SCLK /CS Description DAC C Output DAC D Output Reference Voltage Input (Low) Power Supply Ground Serial Data Input Serial Clock Input Chip-Select Input
Operating Characteristics
Absolute Maximum Ratings
Stresses above those listed may cuuse permanent damage to the device. These are stress ratings only. Functional operation of this device as indicated in this data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.
Parameter Power Supply voltage VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND REFH/REFL Input Voltage OUTx Voltage Maximum Current into Any Pin Continuous Power Dissipation o (TA= + 70 C) QSOP16 Operating Temperature Range Storage Temperature Range
Symbol VDD VI
Min -0.3 -0.3 -0.3 -0.3 -0.3
Typ
P T Tstg -45 -55
Max +7 VDD+0.3 VDD+0.3 VDD+0.3 VDD 50 500 +85 +125
Unit V V V V V mA mW
o o
C C
2
Preliminary
Electrical Characteristics
ZM534
(VDD=+2,7 to +5.5V, VREFH=4V, REFL=GND=0V, RL=10k, CL=100pF,TA=TMIN to TMAX, Typical values are at VDD= +5V and TA= +25oC)
Parameter Static Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Zero-Code Error Zero-Code-Error Supply Rejection Zero Code Temperatur Coefficient Full Scale Error Full-Scale Error Supply Rejection Full-Scale Temperature Coefficient Reference Inputs Input Voltage Range Input Resistance Input Capacitance Channel-to-Channel Isolation AC Feedthrough DAC Outputs Output Voltage Range Load Regulation Digital Inputs Input High Voltage Input Low Voltage Input Current Input Cpacitance Digital Outputs Output High Voltage Output Low Voltage Dynamic Performence Voltage-Output Slew Rate Output Settling Time Digital Feedthrough and Crosstalk
Symbol
Conditions
Min
T yp
Max 8 ±1 ±1 ±20 1
Unit Bits LSB LSB mV LSB µV/ C mV LSB O µV/ C V k pF dB dB V LSB/m A
O
INL DNL
(Note1) Garanteed monotonic (all codes) (Note 1) Code=00 hex Code=00 hex, VDD=4.5 to 5.5V Code=00 hex Code=FF hex Code=FF hex Code=FF hex 0
±10 ±20 1 ±10 VDD 85 10 -60 -60 0 VREFH 0.25
(Note 2) (Note 3) RL=open Code=FF hex, RL from 10k to oo VIH VIL IIN CIN VOH VOL
0.7VDD VIN=0V or VDD (Note 4) ISOURCE=0.1mA ISINK=2mA Code=FF hex To ½ LSB, from code 00 to code FF hex (Note 5) VREFH=0V, code 00 to FF hex (Note 6) Code 80 hex to code 7F hex VREFH=4Vp-p, at 1kHz, code=FF hex/ VREFH=4Vp-p, at 10kHz VREFH=0.5Vp-p, 3dB bandwitdh 0.8 7 4 45 80/70 VDD0.5
V 0.3VDD V µA ±1.0 10 pF V 0.4 V V/µs µs nV-s nV-s dB
Digital-to Analog Glitch Impulse Signal-to-Noise Plus Distorsion Ratio SINAD
Multiplying Bandwidth Wideband Amplifier Noise Power Supplies Power-Supply Voltage Supply Current Shutdown Current
500 60 2,7 1,3 2.5 5.5 10
kHz µVRMS V mA µA
VDD IDD
3