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Part: 182A934
Category:
Memory
-> SRAM
-> 256 Kb
Description: 256K (32K X 8) Space Application
Company: BAE Systems
Datasheet: Download 182A934 datasheet File size : 56 kB
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Datasheet text preview:
32K x 8 Radiation Hardened Static RAM 5 V
Features
167A690 182A934
Product Description
Other · Read/Write Cycle Times 30 ns (-55 °C to 125°C) · SMD Number 5962H92153 · Asynchronous Operation · CMOS or TTL Compatible I/O · Single 5 V ±10% Power Supply · Low Operating Power · Packaging Options · 36-Lead Flat Pack (0.630" x 0.650") · 28-Lead DIP, MIL-STD-1835, CDIP2-T28
Radiation · Fabricated with Bulk CMOS 0.8 µm Process · Total Dose Hardness through 1x106 rad(Si) · Neutron Hardness through 1x1014 N/cm2 · Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s · Soft Error Rate of < 1x10-11 Upsets/Bit-Day · Dose Rate Survivability through 1x1012 rad(Si)/s · Latchup Free
General Description
The 32K x 8 radiation hardened static RAM is a high performance, low power device designed and fabricated in 0.8 µm Radiation Hardened Complementary Metal Oxide Semiconductor (RHCMOS) technology. BAE SYSTEMS' device is designed for radiation environments using industry standard functionality. The memory can be personalized for either CMOS or Transistor Transistor Logic (TTL) input receivers. The SRAM operates over the full military temperature range and requires a single 5 V ±10% power supply. Power consumption is typically less than 20 mW/MHz in operation, and less than 10 mW in the low power disabled mode. The SRAM read operation is fully asynchronous, with an associated typical access time of 20 nanoseconds. BAE SYSTEMS' bulk CMOS technology achieves radiation hardening via a combination of process technology enhancements and specific circuit improvements.
BAE SYSTEMS · 9300 Wellington Road · Manassas, Virginia 20110-4122
Functional Diagram
··· A:11 32,768 x 8 Memory Array ··· Column Decoder Data Input/Output
Row Decoder
E S
W
G
A:4 DQ:8
Signal Definitions
A: 0-14
Address input pins that select a particular eight-bit word within the memory array. Bi-directional data pins that serve as data outputs during a read operation and as data inputs during a write operation.
W
DQ: 0-7
Negative write enable, when at a low level, activates a write operation and holds the data output drivers in a high impedance state. When at a high level, W allows normal read operation. Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by S, W, and E. If this signal is not used it must be connected to GND. Chip enable, when at a high level allows normal operation. When at a low level, E forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the S input buffer. If this signal is not used, it must be connected to VDD.
G S
Negative chip select, when at a low level, allows normal read or write operation. When at a high level, S forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables the data input buffers only. If this signal is not used, it must be connected to GND.
E
Truth Table
Inputs(1),(2) E (4) High High X Low S Low Low High X W Low High X X G X Low X X I/O Data-In Data-Out High-Z High-Z Notes: Power Active Active Standby Standby 1) VIN for don't care (X) inputs = VIL or VIH. 2) When G = high, I/O is high-Z. 3) To dissipate the minimum amount of standby power when in standby mode: S= VDD and E = GND. All other input levels may float. 4) E is tied high internally to the chip for the 28-DIP package.
Mode Write Read Standby Standby(3)
2
Absolute Maximum Ratings
Applied Conditions(1) Storage Temperature Range (Ambient) Operating Temperature Range (TCASE) Positive Supply Voltage Input Voltage(2) Output Voltage(2) Power Dissipation(3) Lead Temperature (Soldering 5 sec) Electrostatic Discharge Sensitivity(4)
Notes:
Minimum -65°C -55°C -0.5 V -0.5 V -0.5 V
Maximum +150°C +125°C +7.0 V VDD+ 0.5 V VDD+ 0.5 V
2.0 W +250°C (Class II)
1) Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. All voltages are with reference to the module ground leads. 2) Maximum applied voltage shall not exceed +7.0 V. 3) Guaranteed by design; not tested. 4) Class as defined in MIL-STD-883, Method 3015.
Recommended Operating Conditions
Symbol VDD GND TC VIL VIH Parameters(1) Supply Voltage Supply Voltage Reference Case Temperature Input Logic "Low" - CMOS Input Logic "Low" - TTL Input Logic "High" - CMOS Input Logic "High" - TTL
Note:
Minimum +4.5 0.0 -55 0.0 0.0 +3.5 +2.0
Maximum +5.5 0.0 +125 +1.5 +0.8 VDD VDD
Units Volt Volt Celsius Volt Volt
1)All voltages referenced to GND.
Power Sequencing
The substrate of this module is connected directly to Ground. Power shall be applied to the device only in the following sequences to prevent damage due to excessive currents: · Power-Up Sequence: GND, VDD, Inputs · Power-Down Sequence: Inputs, VDD, GND
3
DC Electrical Characteristics
Limits Minimum Maximum 180 130 2.0 1.2 2.0 2.0 1.2 2.0 1.0 0.4 1.0 4.2 VDD - 0.5 V 0.4 0.05 2.5 3.5 2.0 1.5 0.8 -5 -10 5 10 4
Test
Symbol
Test Conditions(1) F = FMAX = 1/tAVAV(min) S = VIL = GND E = VIH = VDD No Output Load F = FMAX = 1/tAVAV(min) S = VIH = VDD E = VIL= GND F = FMAX = 1/tAVAV(min) S = VIH = VDD E = VIL= GND VDD= 2.5 V IOH= -4 mA IOH = -200 µA IOL= 8 mA IOL = 200 µA VDD = VDR
Device Type X3X X4X X6X X3X X4X X6X X3X X4X X6X X3X X4X X6X All All All CMOS TTL CMOS TTL
Units mA mA mA mA mA mA mA mA mA mA mA V V V V V µA µA pF
Supply Current (Cycling Selected)
ID D 1
Supply Current (Cycling De-Selected) Supply Current (Standby)
ID D 2
ID D 3
Data Retention Current
ID R
High Level Output Voltage Low Level Output Voltage Data Retention Voltage High Level Input Voltage Low Level Input Voltage Input Leakage Output Leakage Cin
VOH VOL VDR VIH VIL IILK IOLK (2)
0 V VIN 5.5 V 0 V VOUT 5.5 V By Design/ Verified By Characterization By Design/ Verified By Characterization
All All All
Cout
(2)
All
7
pF
Note: 1) Typical operating conditions: VDD = 5.0V; TA = 25 °C, pre-radiation. -55°C Tcase +125°C; 4.5 V VDD 5.5 V; unless otherwise specified. 2) The worst case timing sequence of tWLZQ + tDUWH + tWHWL = tAVAV.
Output Load Circuit
300 ± 10% 2.8V
50 pF + 10%
4
Read Cycle AC Timing Characteristics(1)
Minimum or Maximum Minimum Maximum Minimum Maximum Minimum Maximum Maximum Minimum Maximum Maximum Minimum Maximum Worst Case By Speed -30 -40 -60 30 30 5 30 3 CMOS - 10 TTL - 12 30 3 40 40 5 40 3 15 40 3 60 60 5 60 3 15 60 3 15 15 3 15
Test Read Cycle Time Address Access Time Output Hold After Address Change Chip Select Access Time Chip Select to Output Active Chip Select to Output Disable Chip Enable Access Time Chip Enable to Output Active Chip Disable to Output Disable Output Enable Access Time Output Enable to Output Active Output Enable to Output Disable
Symbol tAVAV tAVQV tAXQX tSLQV tSLQX tSHQZ t EHQV t EHQX tELQZ tGLQV tGLQX tGHQZ
Units ns ns ns ns ns ns ns ns ns ns ns ns
CMOS - 10 15 TTL - 12 CMOS - 12 CMOS - 15 TTL - 18 TTL - 15 3 CMOS - 10 TTL - 12 3 15
Note:
1)Test conditions: input switching levels VIL/VIH = 0.5 V/VDD -0.5 V (CMOS), VIL/VIH = 0 V/3 V (TTL), input rise and fall times 50 pF, derate access times by 0.02 ns/pF (typical). -55 °C Tcase +125°C; 4.5 V VDD 5.5 V; unless otherwise specified.
Read Cycle Timing Diagram
tAVAV
Address
Valid Address
tAVQV tSLQV
S
tAXQX
tSLQX tEHQV
E
tSHQZ
tEHQX tGLQV
G
tELQZ
tGLQX
Data Out
tSHQZ
Valid Data
High Impedance 5
Others parts begin by 18
18-1 18-2
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