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Details, datasheet, quote on part number:190A325
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Datasheet text preview:
128K x 8 Radiation Hardened Static RAM 5 V
Features
190A325 198A592
Product Description
Other · Read/Write Cycle Times 25 ns, 30 ns, 40 ns (-55 to 125°C) · SMD Number 5962H96877 · Asynchronous Operation · CMOS or TTL Compatible I/O · Single 5 V ±10% Power Supply · Low Operating Power · Packaging Options · 40-Lead Flat Pack (0.775" x 0.710") · 40-Lead Flat Pack - Small Cavity (0.775" x 0.650") 32-Lead Flat Pack (0.652" x 0.820")
Radiation · Fabricated with Bulk CMOS 0.5 µm Process · Total Dose Hardness through 1x106 rad(Si) · Neutron Hardness through 1x1014 N/cm2 · Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s · Soft Error Rate of < 1x10-11 Upsets/Bit-Day · Dose Rate Survivability through 1x1012 rad(Si)/s · Latchup Free
General Description
The 128K x 8 radiation hardened static RAM is a high performance 131,072 word x 8-bit static random access memory with industrystandard functionality. It is fabricated with BAE SYSTEMS' radiation hardened technology and is designed for use in systems operating in radiation environments. The RAM operates over the full military temperature range and requires a single 5 V ±10% power supply. The RAM is available with either TTL or CMOS compatible I/O. Power consumption is typically less than 20 mW/MHz in operation, and less than 10 mW in the low power disabled mode. The RAM read operation is fully asynchronous, with an associated typical access time of 19 nanoseconds. BAE SYSTEMS' enhanced bulk CMOS technology is radiation hardened through the use of advanced and proprietary design, layout, and process hardening techniques.
BAE SYSTEMS · 9300 Wellington Road · Manassas, Virginia 20110-4122
Functional Diagram
A0
Top/Bottom Decoder
A1 - A2
Block Address Decoder
A3
L/R Side/Block
A9 - A16
Row Address Decoder
((256 x 32) x 2 x 4) x 8 x 2 Memory Cell Array
8 Bit Word Input/Output
W
Column Address Decoder
G
E S
DQ0-DQ7
A4-A8
Signal Definitions
A: 0-16
Address input pins that select a particular eight-bit word within the memory array. Bi-directional data pins that serve as data outputs during a read operation and as data inputs during a write operation. Negative chip select, when at a low level, allows normal read or write operation. When at a high level, S forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables the data input buffers only. If this signal is not used, it must be connected to GND.
W
DQ: 0-7
Negative write enable, when at a low level, activates a write operation and holds the data output drivers in a high impedance state. When at a high level, W allows normal read operation. Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by S, W, and E. If this signal is not used it must be connected to GND. Chip enable, when at a high level allows normal operation. When at a low level, E forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the S input buffer. If this signal is not used, it must be connected to VDD.
G
S
E
Truth Table
Inputs(1),(2) E S W G I/O
Notes:
Power
Mode
1) VIN for don't care (X) inputs = VIL or VIH. Active Active Standby Standby 2) When G = high, I/O is high-Z. 3) To dissipate the minimum amount of standby power when in standby mode: S= VDD and E = GND. All other input levels may float.
Write Read Standby Standby(3)
High High X Low
Low Low High X
Low High X X
X Low X X
Data-In Data-Out High-Z High-Z
2
Absolute Maximum Ratings
Applied Conditions(1) Minimum Maximum
Storage Temperature Range (Ambient) Operating Temperature Range Positive Supply Voltage Input Voltage(2) Output Voltage(2) Power Dissipation(3) Lead Temperature (Soldering 5 sec) Electrostatic Discharge Sensitivity(4)
Notes:
-65°C -55°C -0.5 V -0.5 V -0.5 V
+150°C +125°C +7.0 V VDD+ 0.5 V VDD+ 0.5 V
2.0 W +250°C (Class II)
1) Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. All voltages are with reference to the module ground leads. 2) Maximum applied voltage shall not exceed +7.0 V. 3) Guaranteed by design; not tested. 4) Class as defined in MIL-STD-883, Method 3015.
Recommended Operating Conditions
Symbol Parameters(1) Minimum Maximum Units
VDD GND TC VIL VIH
Supply Voltage Supply Voltage Reference Case Temperature Input Logic "Low" - CMOS Input Logic "Low" - TTL Input Logic "High" - CMOS Input Logic "High" - TTL
Note:
+4.5 0.0 -55 0.0 0.0 +3.5 +2.0
+5.5 0.0 +125 +1.5 +0.8 VDD VDD
Volt Volt Celsius Volt Volt
1)All voltages referenced to GND.
Power Sequencing
The substrate of this module is connected directly to Ground. Power shall be applied to the device only in the following sequences to prevent damage due to excessive currents: · Power-Up Sequence: GND, VDD, Inputs · Power-Down Sequence: Inputs, VDD, GND
3
DC Electrical Characteristics
Limits Minimum Maximum
Test
Symbol
Test Conditions(1)
Device Type
Units
Supply Current (Cycling Selected)
ID D 1
F = FMAX = 1/tAVAV(min) S = VIL = GND E = VIH = VDD No Output Load F = FMAX = 1/tAVAV(min) S = VIH = VDD E = VIL= GND F = 0 MHz S = VIH = VDD E = VIL= GND VDD= 2.5 V IOH= -4 mA IOH = -200 µA IOL= 8 mA IOL = 200 µA VDD = VDR CMOS TTL CMOS TTL 0 V VIN 5.5 V 0 V VOUT 5.5 V By Design/ Verified By Characterization By Design/ Verified By Characterization
All
180
mA
Supply Current (Cycling De-Selected) Supply Current (Standby)
ID D 2
All
2.0
mA
ID D 3
All
2.0
mA
Data Retention Current
ID R
All 4.0 VDD - 0.5 V
1.0
mA
High Level Output Voltage Low Level Output Voltage Data Retention Voltage High Level Input Voltage Low Level Input Voltage Input Leakage Output Leakage Cin
VOH VOL VDR VIH VIL IILK IOLK (2)
All All All All All All All All
V 0.4 0.05 V V V 1.5 0.8 V µA µA pF
2.5 3.5 2.0
-5 -10
5 10 7
Cout
(2)
All
10
pF
Note:
1) Typical operating conditions: -55 °C Tcase +125°C; 4.5 V VDD 5.5 V; unless otherwise specified. 2) Guaranteed by design and verified by periodic characterization.
Output Load Circuit
300 ± 10% 2.8V
50 pF + 10%
4
Read Cycle AC Timing Characteristics(1)
Minimum or Maximum Worst Case By Speed -25 -30 -40
Test
Symbol
Units
Read Cycle Time Address Access Time Output Hold After Address Change Chip Select Access Time Chip Select to Output Active Chip Select to Output Disable Chip Enable Access Time Chip Enable to Output Active Chip Disable to Output Disable Output Enable Access Time Output Enable to Output Active Output Enable to Output Disable
Note:
tAVAV tAVQV tAXQX tSLQV tSLQX tSHQZ t EHQV t EHQX tELQZ tGLQV tGLQX tGHQZ
Minimum Maximum Minimum Maximum Minimum Maximum Maximum Minimum Maximum Maximum Minimum Maximum
25 25
30 30
40 40
ns ns ns ns ns ns ns ns ns ns ns ns
40FP - 0 40FP - 0 40FP - 0 32FP - 2 32FP - 2 32FP - 2 25 0 12 25 0 12 10 0 12 30 0 12 30 0 12 12 0 12 40 0 15 40 0 15 15 0 15
1)Test conditions: input switching levels VIL/VIH = 0.5 V/VDD -0.5 V (CMOS), VIL/VIH = 0 V/3 V (TTL), input rise and fall times 50 pF, derate access times by 0.02 ns/pF (typical). -55°C Tcase +125°C; 4.5 V VDD 5.5 V; unless otherwise specified.
Read Cycle Timing Diagram
tAVAV
Address
Valid Address
tAVQV tSLQV
S
tAXQX
tSLQX tEHQV
E
tSHQZ
tEHQX tGLQV
G
tELQZ
tGLQX
Data Out
tSHQZ
Valid Data
High Impedance
5
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