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Details, datasheet, quote on part number:238A790
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Datasheet text preview:
32K x 8 Radiation Hardened Programmable Read Only Memory (PROM) 3.3V
Features
238A790
Product Description
Other · Read/Write Cycle Times 100 ns (-55 °C to 125°C) · SMD Number Pending · Asynchronous Operation · TTL Compatible I/O · Single 3.3 V ±5% Power Supply · Low Operating Power · Packaging Options · 28-Lead Flat Pack (0.500" x 0.720")
Radiation · Fabricated with Bulk CMOS 0.8 µm Process · Total Dose Hardness through 2x105 rad(Si) · Neutron Hardness through 1x1012 N/cm2 · SEU Immune (No Latches) · Latchup Free
General Description The 32K x 8 radiation hardened PROM is pinout, function and package compatible with commercial 28C256 series 32K x 8 EEPROMs, such as SEEQ 28C256 and Atmel AT28C256. The PROM is fabricated with BAE SYSTEMS' QML-qualified radiation hardened technology, and is designed for use in systems operating in radiation environments. The radiation hardened Oxide-Nitride-Oxide (ONO) anti-fuse technology features 0.8 micron, 5 V transistors in the data path, and 1.0 micron, high voltage N and PFETs in the programming path circuitry. The PROM operates over the full military temperature range, requires a single 3.3 V ± 5% power supply, and is available with TTL compatible I/O. Power consumption is typically 15 mW/MHz in operation and is less than 10 mW/MHz in the low power disabled mode. The PROM operation is fully asynchronous, with an associated typical access time of 100 nanoseconds. Synchronous operation is also possible using CE as a clock. BAE SYSTEMS' enhanced bulk CMOS technology is radiation hardened through the use of advanced and proprietary design, layout, and process hardening techniques.
BAE SYSTEMS · 9300 Wellington Road · Manassas, Virginia 20110-4122
Functional Diagram
A5 - A11
Row Decoders
Memory Array
A0 - A4 A12 - A14 CE OE VPP*
Column Decoders Section Select
Column Muxing and Sense Amps
Control Logic
I/O Buffers
DQ0 - 7 *PROM Programming Voltage
Signal Definitions
A: 0-14
Address input pins that select a particular eight-bit word within the memory array. Bi-directional data pins that serve as data outputs during a read operation and as data inputs during a write operation. Negative output enable, when at a high level, holds the data output drivers in a high impedance state. In programming mode, with OE high and CE low, data driver state is in "Data-In" to enable programming.
CE
DQ: 0-7
Chip enable, when at a low level with OE at low level, allows normal operation. When at a high level, CE forces the data output drivers in a high impedance state.
OE
Truth Table
Mode Read Tristate Standby Standby Program (4) Inputs(1),(2) CE Low Low VDD High Low OE Low High X X High VPP VDD VDD VDD VDD 17V ± 0.5V I/O Data-Out High-Z High-Z High-Z Data-In Power (3) Active Active Standby1 Standby2 Programming
Notes: 1) VIN for don't care (X) inputs = VIL or VIH. 2) High: VIN 2.2 V for TTL inputs. Low: VIN 0.8 V for TTL inputs. 3) Minimum IDD is drawn when standby mode is implemented with CE = VDD(standby1 power). 4) Programming needs to be done using VDD = 5V.
2
Absolute Maximum Ratings
Applied Conditions(1) Storage Temperature Range (Ambient) Operating Temperature Range Positive Supply Voltage Input Voltage(2) Output Voltage(2) Power Dissipation(3) Lead Temperature (Soldering 5 sec) Electrostatic Discharge Sensitivity(4)
Notes:
Minimum -65°C -55°C -0.5 V -0.5 V -0.5 V
Maximum +150°C +125°C +7.0 V VDD+ 0.5 V VDD+ 0.5 V 1.5 W +250°C
(Class I)
1) Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. All voltages are with reference to the module ground leads. 2) Maximum applied voltage shall not exceed +7.0 V. 3) Guaranteed by design; not tested. 4) Class as defined in MIL-STD-883, Method 3015.
Recommended Operating Conditions
Symbol VDD VPP GND TC VIL VIH Parameters(1) Supply Voltage Programming Voltage Supply Voltage Reference Case Temperature Input Logic "Low" - TTL Input Logic "High" - TTL Minimum +3.14 VDD (2) 0.0 -55 0.0 +2.2 Maximum +3.46 VDD (2) 0.0 +125 +0.8 VDD Units Volt Volt Volt Celsius Volt Volt
Notes:
1) All voltages referenced to GND. 2) VPP = VDD during non-programming mode.
Power Sequencing
Power shall be applied to the device only in the following sequences to prevent damage due to excessive currents: · Power-Up Sequence: GND, VDD, Inputs · Power-Down Sequence: Inputs, VDD, GND
3
DC Electrical Characteristics
Limits Test Supply Current (Cycling Selected) Supply Current (Standby) High Level Output Voltage Low Level Output Voltage High Level Input Voltage TTL Inputs Low Level Input Voltage TTL Inputs Symbol Test Conditions(1) F = FMAX = 1/tAVAV(min) CMOS Input No Output Load F = FMAX = 1/tAVAV(min) CE = VPP = VIH = VDD IOH= -2 mA IOH = -200 µA IOL= 4 mA IOL = 200 µA Group A Subgroups 1, 2, 3 Device Type (2) All Minimum Maximum 150 Units
ID D 1
mA
ID D 2 VOH VOL VIH VIL
1, 2, 3
All 2.4 VDD - 0.1 V
2.0
mA
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
All All All All
V 0.4 0.1 V V 0.8 V
2.2
Input Leakage
IILK
0 V VIN 5.5 V 0 V VOUT 5.5 V
1, 2, 3
All
-5
5
µA
Output Leakage Cin Cout
IOLK
1, 2, 3 4 4
All All All
-10
10 7 10
µA pF pF
Note: 1) -55 °C Tcase +125°C; 3.14 V VDD 3.46 V; unless otherwise specified. Test conditions for AC measurements: 2) Measured during initial device characterization.
· Input Levels · Input Rise and Fall Time · Input and Output Timing Reference Levels (Except for Tristate Parameters) · Input and Output Timing Reference Levels or Tristate Parameters · Programmed Array Mix of `1's and `0's · Output Load · Read Cycle
0 V to VDD 2.0 ns/Volt 1.5 V
VOL = 1.23 V; VOH = 2.23 V 50%
Output Load Circuit
167 ± 10% 1.73V
See Output Load Circuit Diagram See Read Cycle Timing
50 pF ± 10%
4
Read Cycle AC Timing Characteristics (1)
Limits Minimum Maximum 100
Test Read Cycle Time Address Access Time
Symbol tAVAV tAVQV
Device Type
Units ns ns
ALL
ALL Chip Enable Access Time tELQV ALL Output Enable Access Time Chip Enable to Output Active Output Enable to Output Active Output Hold After Address Change Chip Enable to Output Disable Output Enable to Output Disable
Note:
100 ns 100 100 0 0 0 15 15 ns ns ns ns ns ns
tGLQV tELQX tGLQX tAXQX tEHQZ tGHQZ
ALL
1) -55°C Tcase +125°C; 3.14 V VDD 3.46 V; unless otherwise specified.
Read Cycle Timing Diagram
t AVAV
Address
Valid Address t AVQV tELQV tAXQX
CE
tELQX tGLQV
OE
tEHQZ
tGLQX
Data Out
tGHQZ
Valid Data High Impedance
5
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