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Details, datasheet, quote on part number:238A792
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Datasheet text preview:
128K x 32 Radiation Hardened Static RAM MCM 3.3V
Features
238A792
Product Description
Other · Read/Write Cycle Times 35 ns (-55 °C to 125°C) · SMD Number Pending · Asynchronous Operation · TTL Compatible I/O · Single 3.3 V ± 10% Power Supply · Low Operating Power · Packaging Options · 64-Lead Dual Flat Pack (1.000" x 0.900")
Radiation · Fabricated with Bulk CMOS 0.5 µm Process · Total Dose Hardness through 1x106 rad(Si) · Neutron Hardness through 1x1014 N/cm2 · Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s · Soft Error Rate of < 1x10-11 Upsets/Bit-Day · Latchup Free
General Description
The 128K x 32 radiation hardened static RAM is composed of four 128K x 8 SRAM memory die assembled in a single, doublesided ceramic substrate. Each die is a high performance 131,072 word x 8-bit static random access memory with industrystandard functionality. It is fabricated with BAE SYSTEMS' radiation hardened technology and is designed for use in systems operating in radiation environments. The RAM operates over the full military temperature range and requires a single 3.3 V ± 10% power supply. The RAM is available with CMOS compatible I/O. Power consumption is typically less than 80 mW/MHz in operation, and less than 40 mW in the low power disabled mode. The RAM read operation is fully asynchronous, with an associated typical access time of 19 nanoseconds. BAE SYSTEMS' enhanced bulk CMOS technology is radiation hardened through the use of advanced and proprietary design, layout, and process hardening techniques.
BAE SYSTEMS · 9300 Wellington Road · Manassas, Virginia 20110-4122
Functional Diagram
A0
Top/Bottom Decoder
A1 - A2
Block Address Decoder
A3
L/R Side/Block
A9 - A16
(((256 x 32) x 2 x 4) x 8 x 2) x 4
Row Address Decoder
Memory Cell Array
32 Bit Word Input/Output
W
Column Address Decoder
G
S1 - S4
DQ0-DQ31
Note:
A4-A8
1) All package leads are common with top and bottom SRAM devices except for S1 through S4.
Signal Definitions
A: 0-16
Address input pins that select a particular eight-bit word within the memory array. Bi-directional data pins that serve as data outputs during a read operation and as data inputs during a write operation. Negative chip select, when at a low level, allows normal read or write operation. When at a high level, S1 through S4 forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables the data input buffers only. If this signal is not used, it must be connected to GND.
W
DQ: 0-31
Negative write enable, when at a low level, activates a write operation and holds the data output drivers in a high impedance state. When at a high level, W allows normal read operation. Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by S1 through S4, and W. If this signal is not used it must be connected to GND.
G
S1 - S4
Truth Table
Inputs(1),(2) S1 - S4 W G I/O
Notes:
Power
Mode
1) VIN for don't care (X) inputs = VIL or VIH. Active Active Standby 2) When G = high, I/O is high-Z. 3) To dissipate the minimum amount of standby power when in standby mode: S1 = S2 = S3 = S4 = VDD. All other input levels may float.
Write Read Standby(3)
Low Low High
Low High X
X Low X
Data-In Data-Out High-Z
2
Absolute Maximum Ratings
Applied Conditions(1) Minimum Maximum
Storage Temperature Range (Ambient) Operating Temperature Range (Tcase) Positive Supply Voltage Input Voltage (2) Output Voltage (2) Power Dissipation (3) Lead Temperature (Soldering 5 sec) Thermal Resistance, Junction-to-Case (JC) (6) Electrostatic Discharge Sensitivity (4)
-65°C -55°C -0.5 V -0.5 V -0.5 V
+150°C +125°C +5.5 V VDD+ 0.5 V VDD+ 0.5 V
2.5 W (5) 13.0°C/W +230°C (Class II)
Notes:
1) Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. All voltages are with reference to the module ground leads. 2) Maximum applied voltage shall not exceed +5.5 V. 3) Guaranteed by design; not tested. 4) Class as defined in MIL-STD-883, Method 3015. 5) Typical power dissipation = 2.0 W. 6) It is recommended that the part be thermally bonded to the board.
Recommended Operating Conditions
Symbol Parameters(1) Minimum Maximum Units
VDD GND TC VIL VIH
Supply Voltage Supply Voltage Reference Case Temperature Input Logic "Low" Input Logic "High"
Note:
+3.14 0.0 -55 -0.3 +2.0
+3.46 0.0 +125 +0.8 VDD
Volt Volt Celsius Volt Volt
1)All voltages referenced to GND.
Power Sequencing
Power shall be applied to the device only in the following sequences to prevent damage due to excessive currents: · Power-Up Sequence: GND, VDD, Inputs · Power-Down Sequence: Inputs, VDD, GND
3
DC Electrical Characteristics
Group A Sub-Groups Device Type Limits Minimum Maximum
Test
Symbol
Test Conditions(1)
Units
Supply Current (Cycling Selected) Supply Current (Cycling De-Selected) Supply Current (Standby) Data Retention Current High Level Output Voltage Low Level Output Voltage Data Retention Voltage High Level Input Voltage Low Level Input Voltage Input Leakage Output Leakage Cin Cout
ID D 1 ID D 2 ID D 3 ID R VOH VOL VDR (3) VIH VIL IILK IOLK
F = FMAX = 1/tAVAV(min) No Output Load F = FMAX = 1/tAVAV(min) S1 = S2 = S3 = S4 = VDD F = 0 MHz S1 = S2 = S3 = S4 = VDD VDD= 1.5 V IOH= -4 mA IOH = -200 µA IOL= 8 mA IOL = 200 µA VDD= VDR TTL TTL 0 V VIN 3.46 V 0 V VOUT 3.46 V
(2)
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
All All
720 8.0
mA mA
All All All All All All All All All All All -20 -40 1.5 2.0 2.4 VDD - 0.1 V
8.0 7.2
mA mA V
0.4 0.05
V V V
0.8 20 40 50 40
V µA µA pF pF
(2)
Notes:
1) Typical operating conditions: Vdd 5.0 V; TA = 25°C, pre-radiation. -55°C Tcase +125°C; 3.14 V VDD 3.46 V; unless otherwise specified. 2) By Design / Verified by Characterization 3) The worst case timing sequence of tWLQZ + tDVWH + tWHWL = tAVAV (write cycle time)
Output Load Circuit
167 ± 10% 1.73V
50 pF + 10%
4
Read Cycle AC Timing Characteristics(1)
Minimum or Maximum Minimum Maximum Maximum Maximum Minimum Minimum Minimum Maximum Maximum
Test Read Cycle Time Address Access Time Chip Select Access Time Output Enable Access Time Chip Select to Output Active Output Enable to Output Active Output Hold After Address Change Chip Select to Output Disable Output Enable to Output Disable
Symbol tAVAV tAVQV tSLQV tGLQV tSLQX tGLQX tAXQX tSHQZ tGHQZ
Device Type X3X X4X X3X X4X X3X X4X X3X X4X All All All All All
Limits 35 40 35 40 35 40 15 15 0 0 0 15 15
Units ns ns ns ns ns ns ns ns ns
Note: 1)Test conditions: input switching levels VIL/VIH = 0.5 V/VDD -0.5 V (CMOS), input rise and fall times 50 pF, derate access times by 0.02 ns/pF (typical). -55 °C Tcase +125°C; 3.14 V VDD 3.46 V; unless otherwise specified.
Read Cycle Timing Diagram
tAVAV
Address
Valid Address
tAVQV tSLQV
S1 - S4
tAXQX
tSLQX
tSHQZ tGLQV
G
tGLQX
Data Out
tSHQZ
Valid Data
High Impedance
5
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