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Details, datasheet, quote on part number:MTV016
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Datasheet text preview:
MYSON TECHNOLOGY
FEATURES
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MTV016
Enhanced On-Screen-Display Controller
Horizontal SYNC input up to 100 KHz. On-chip PLL circuitry up to a 90 MHz pixel rate for multi-SYNC operation. Programmable horizontal resolutions up to 1524 dots per display row. 538-byte display registers to control full screen display. Full screen display consists of 10 (rows) by 24 (columns) characters. 12 x 18 dot matrix per character. 128 built-in characters and graphic symbols, and character by character color selection. Maximum of 8 colors selectable per display row. Double character height and/or width control. Programmable positioning for display screen center. Bordering and shadowing effect for display. Programmable vertical character height (18 to 71 lines) for multi-SYNC operation. 4 programmable background windows with multi-level windowing effect. Software clear function for display frame buffer. HSYNC and VSYNC input polarity selectable. Auto detection for input edge distortion between HSYNC and VSYNC inputs. Half tone and fast blanking output. Software force blank function for display frame. Compatible with both SPI bus and I2C interface through pin selection. 16-pin PDIP package.
GENERAL DESCRIPTION
MTV016 is designed for use in monitor applications to display the built-in characters or symbols onto a monitor screen. The display operation occurs by transferring data and control information in the microcontroller to RAM through a serial data interface. It can execute a full screen display automatically and specific functions such as character bordering, shadowing, double height and width, font by font color control, frame positioning, frame size control by character height and horizontal display resolution, and windowing effect.
BLOCK DIAGRAM
SSB 8DATA SCK DATA 5 CWS CHS
SERIAL DATA INTERFACE
DAEN 2RAEN,CAEN
DISPLAY & ROW CONTROL REGISTERS
CCS0 CCS1 BLINK 7 CRADDR
VDD VSS
SDA 5 RCADDR ARWDB HDREN VDREN NROW LUMA LPN CWS VCLKS VFLB VSP CH 7 CHS VERTD 8 5 LPN NROW VDREN DATA 8 8 VERTD 8 HORD 7 CH 5
VDDA VSSA
ADDRESS BUS ADMINISTRATOR
CHARACTER ROM LUMINANCE & BORDGER GENERATOR
9 DADDR 5 WADDR
BORDER
VERTICAL DISPLAY CONTROL
HORIZONTAL DISPLAY CONTROL PHASE LOCK LOOP
WINDOWS & FRAME CONTROL
WR WG WB CCS2 FBKGC BLANK
BSEN SHADOW OSDENB HSP VSP
HFLB HSP RP VCO HORD 7
ARWDB HDREN VCLKX CCS0 CCS1 BLINK VCLKX
ROUT GOUT BOUT FBKG HTONE
COLOUR ENCODER
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. MTV016 Revision 2.0 01/01/1999
1/11
MYSON TECHNOLOGY
1.0 CONNECTION DIAGRAM
(16-PIN PDIP 300 MIL PACKAGE)
MTV016
VSSA VCO RP VDDA HFLB SSB SDA SCK
1 2 3 4 5 6 7 8
16 15 14 13
VSS ROUT GOUT BOUT FBKG HTONE VFLB VDD
MTV016-N
12 11 10 9
2.0 PIN DESCRIPTIONS
Name VSSA VCO RP VDDA HFLB SSB SDA SCK VDD VFLB HT ONE FBKG BOUT GOUT ROUT VSS I/O I/O I/O I I I I I O O O O O Pin# Function 1 Analog Ground. Used for internal analog circuitry. 2 Voltage Control Oscillator. Used to control the internal oscillator frequency by DC voltage input from an external low pass filter. 3 Bias Resistor. Used to regulate the appropriate bias current for the internal oscillator to resonate at a specific dot frequency. 4 Analog Power Supply. Positive 5 V DC supplies for internal analog circuitry. A 0.1uF decoupling capacitor should be connected across VDDA and VSSA. 5 Horizontal Input. Used to input the horizontal synchronizing signal. It is negative edge triggered and has an internal 100 k pull-up resistor. 6 Serial Interface Enable. Used to enable the serial data and to select I2C or SPI bus operation. If this pin is left floating, the I2C bus is enabled, otherwise the SPI bus is enabled. 7 Serial Data Input. Transfers data through this pin to the internal display and control registers. It has an internal 100 k pull-up resistor. 8 Serial Clock Input. Used to synchronize the data transfer. It has an internal 100 k pull-up resistor. 9 Digital Power Supply. Positive 5 V DC supply for internal digital circuitry and a 0.1uF decoupling capacitor should be connected across VDD and VSS. 10 Vertical Input. Used to input the vertical synchronizing signal. It is negative triggered and has an internal pull-up resistor. 11 Half Tone Output. Used to attenuate the external R, G, B amplifiers gain for the transparent windowing effect. 12 Fast Blanking Output. Used to cut off the external R, G, B signals while this chip is displaying characters or windows. 13 Blue Color Output. A blue color video signal output. 14 Green color output. It is a green color video signal output. 15 Red Color Output. A red color video signal output. 16 Digital Ground. Used for internal digital circuitry.
MTV016 Revision 2.0 01/01/1999 2/11
MYSON TECHNOLOGY
3.0 FUNCTIONAL DESCRIPTIONS
3.1 Serial Data Interface
MTV016
The serial data interface receives data transmitted from an external controller. There are 2 types of bus that can be accessed through the serial data interface: SPI bus and I2C bus. 3.1.1 SPI Bus W hile SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. A valid transmission should be started by pulling SSB to "low" level, enabling MTV016 in receiving mode, and retaining "low" level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 2:
SSB SCK SDA MS B
first byte last byte
LSB
Figure 2. Data Transmission Protocol There are 3 transmission formats as shown below: Format (a) R - C - D R - C - D R - C - D .......... Format (b) R - C - D C - D C - D C - D ....... Format (c) R - C - D D D D D D ......... R=row address, C=column address, D=display data 3.1.2 I2C Bus The I2C bus operation is only selected when the SSB pin is left floating. A valid transmission should begin by writing the slave address 7AH, which is the mask option, to MTV016. The protocol is shown in Figure 3:
SCK
SDA
START
B7
B6
fist byte
B0
ACK
B7
second byte
B0
ACK last byte STOP
Figure 3. Data Transmission Protocol (I2C) There are 3 transmission formats as shown below: Format (a) S - R - C - D R - C - D R - C - D .......... Format (b) S - R - C - D C - D C - D C - D ....... Format (c) S - R - C - D D D D D D ........ S=slave address, R=row address, C=column address, D=display data Each arbitrary length of data packet consists of 3 portions: row address (R), column address (C) and display data (D). Format (a) is suitable for updating small amounts of data, which will be allocated to different row and column addresses. Format (b) is recommended for updating data that has the same row address but a different column address. Massive data updating or a full screen data change should use format (c) to increase transmission efficiency. The row and column address will be incremented automatically when format (c) is applied. Furthermore, the undefined locations in display or font RAM should be filled with dummy data.
MTV016 Revision 2.0 01/01/1999 3/11
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