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Details, datasheet, quote on part number:MTV021
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Datasheet text preview:
MYSON TECH NOLOGY
FEATURES
· Horizontal SYNC input up to 130 KHz. · On-chip PLL circuitry up to 96 MHz. · Programmable horizontal resolutions up to 1524 dots per display row. · Full-screen display consists of 15 (rows) by 30 (columns) characters. · 12 x 18 dot matrices per character. · Total of 272 characters and graphic fonts, including 256 standard and 16 multi-color mask ROM fonts. · 8 color-selectable maximum per display character. · 7 color-selectable maximum for character background. · Double character height and/or width control. · Programmable positioning for display screen center. · Bordering, shadowing and blinking effect. · Programmable character height (18 to 71 lines) control. · Row to row spacing register to manipulate the constant display height. · 4 programmable background windows with multi-level operation and shadowing on window effect. · Software clears bit for full-screen erasing. · Half tone and fast blanking output. · Fade-in/fade-out effect. · 8-channel/8-bit PWM D/A converter output. · Compatible with SPI bus or I2C interface with slave address 7AH (slave address is mask option). · 16-pin, 20-pin or 24-pin PDIP package.
MTV021
Enhanced Super On-Screen Display
GENERAL DESCRIPTION
MTV021 is designed for monitor applications to display built-in characters or fonts onto monitor screens. The display operation occurs by transferring data and control information from the micro-controller to RAM through a serial data interface. It can execute full-screen display automatically, as well as specific functions such as character background color, bordering, shadowing, blinking, double height and width, font by font color control, frame positioning, frame size control by character height and row-to-row spacing, horizontal display resolution, full-screen erasing, fade-in/fade-out effect, windowing effect and shadowing on window. MTV021 provides 256 standard and 16 multi-color characters and graphic fonts for more efficacious applications. The full OSD menu is formed by 15 rows x 30 columns, which can be positioned anywhere on the monitor screen by changing vertical or horizontal delay. Moreover, MTV021 also provides 8 PWM DAC channels with 8-bit resolution and a PWM clock output for external digital-to-analog control.
BLOCK DIAGRAM
SSB 8 DATA SCK DATA 8 CWS CHS LUMAR LUMAG LUMAB BLINK 8 CRADDR VDD VSS
SERIAL DATA INTERFACE
9 ROW, COL ACK
DISPLAY & ROW CONTROL REGISTERS
SDA 5 RCADDR 9 DADDR 9 FONTADDR 5 WINADDR 5 PWMADDR DATA LPN CWS VCLKS VFLB VSP CH 7 CHS VERTD 8 5 LPN NROW VDREN DATA 8 8 VERTD 8 HORD 7 CH 8 5
VDDA
CHARACTER ROM LUMINANCE & BORDGER GENERATOR
LUMA BORDER VSSA
ARWDB HDREN VDREN NROW
ADDRESS BUS ADMINISTRATOR
VERTICAL DISPLAY CONTROL
HORIZONTAL DISPLAY CONTROL PHASE LOCK LOOP
WINDOWS & FRAME CONTROL
WR WG WB FBKGC BLANK
BSEN SHADOW OSDENB HSP VSP
HFLB HSP RP VCO PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 HORD 8
ARWDB HDREN VCLKX LUMAR LUMAG LUMAB BLINK VCLKX
ROUT GOUT BOUT FBKG HTONE
COLOUR ENCODER
PWM D/A CONVERTER
8 DATA
POWER ON RESET
PRB
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product. 1/17 MTV021 Revision 6.0 10/21/1999
MYSON TECH NOLOGY
1.0 PIN CONNECTION
VSSA V CO RP VDDA HF LB SSB SDA SCK
1 2 3 16 15 14
MTV021
VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VF LB VDD
VSSA VCO RP VDDA HF LB SSB SDA SCK PWM0 PWM1
1 2 3 4
20 19 18 17
VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VF LB VDD PWM7 PWM6
VSSA V CO RP VDDA HFLB SSB SDA SCK PWM0 PWM1 PWM2 PWM3
1 2 3 4 5
24 23 22 21 20
VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VF LB VDD PWM7 PWM6 PWM5 PWM4
MT V021N
4 5 6 7 8
13 12 11 10 9
MT V02 1 N20
5 6 7 8 9 10
16 15 14 13 12 11
MTV021N24
6 7 8 9 10 11 12
19 18 17 16 15 14 13
2.0 PIN DESCRIPTIONS
Name VSSA VCO RP V DDA I/O I/O I/O Pin No. N 1 2 3 4 N20 N24 1 2 3 4 1 2 3 4 Descriptions Analog ground. This ground pin is used to internal analog circuitry. Voltage Control Oscillator. This pin is used to control the internal oscillator frequency by DC voltage input from external low pass filter. Bias Resistor. The bias resistor is used to regulate the appropriate bias current for internal oscillator to resonate at specific dot frequency. Analog power supply. Positive 5 V DC supply for internal analog circuitry. And a 0.1uF decoupling capacitor should be connected across to VDDA and VSSA. Horizontal input. This pin is used to input the horizontal synchronizing signal. It is a leading edge triggered and has an internal pull-up resistor. Serial interface enable. It is used to enable the serial data and is also used to select the operation of I2C or SPI bus. If this pin is left floating, I2C bus is enabled, otherwise the SPI bus is enabled. Serial data input. The external data transfer through this pin to internal display registers and control registers. It has an internal pull-up resistor. Serial clock input. The clock-input pin is used to synchronize the data transfer. It has an internal pull-up resistor. Open-Drain PWM D/A converter 0. The output pulse width is programmable by the register of Row 15, Column 23. Open-Drain PWM D/A converter 1. The output pulse width is programmable by the register of Row 15, Column 24. Open-Drain PWM D/A converter 2. The output pulse width is programmable by the register of Row 15, Column 25. Open-Drain PWM D/A converter 3. The output pulse width is programmable by the register of Row 15, Column 26.
HFLB SSB
I I
5 6
5 6
5 6
SDA SCK PWM0 PWM1 PWM2 PWM3
I I O O O O
7 8 -
7 8 9 10 -
7 8 9 10 11 12
2/17
MTV021 Revision 6.0 10/21/1999
MYSON TECH NOLOGY
Name PWM4 PWM5 PWM6 PWM7 V DD I/O O O O O Pin No. N 9 N20 N24 11 12 13 13 14 15 16 17 Descriptions
MTV021
Open-Drain PWM D/A converter 4. The output pulse width is programmable by the register of Row 15, Column 27. Open-Drain PWM D/A converter 5. The output pulse width is programmable by the register of Row 15, Column 28. Open-Drain PWM D/A converter 6. The output pulse width is programmable by the register of Row 15, Column 29. Open-Drain PWM D/A converter 7. The output pulse width is programmable by the register of Row 15, Column 30. Digital power supply. Positive 5 V DC supply for internal digital circuitry and a 0.1uF decoupling capacitor should be connected across to VDD and VSS. Vertical input. This pin is used to input the vertical synchronizing signal. It is leading triggered and has an internal pull-up resistor. Half tone output / PWM clock output. This is a multiplexed pin selected by PWMCK bit. This pin can be a PWM clock or used to attenuate R, G, B gain of VGA for the transparent windowing effect. Fast Blanking output. It is used to cut off external R, G, B signals of VGA while this chip is displaying characters or windows. Blue color output. It is a blue color video signal output. Green color output. It is a green color video signal output. Red color output. It is a red color video signal output. Digital ground. This ground pin is used to internal digital circuitry.
VFLB HTONE / PWMCK FBKG B O UT GOUT ROUT VSS
I O
10 11
14 15
18 19
O O O O -
12 13 14 15 16
16 17 18 19 20
20 21 22 23 24
3.0 FUNCTIONAL DESCRIPTIONS
3.1 SERIAL DATA INTERFACE
The serial data interface receives data transmitted from an external controller. And there are 2 types of bus can be accessed through the serial data interface, one is SPI bus and other is I2C bus. 3.1.1 SPI bus While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission should be starting from pulling SSB to "low" level, enabling MTV021 to receiving mode, and retain "low" level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.
SSB SCK SDA MS B
first byte last byte
LSB
FIGURE 1. Data Transmission Protocol (SPI)
3/17 MTV021 Revision 6.0 10/21/1999
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