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Part: MTV112A16
Category:
Microcontrollers
-> Monitor Controller
Description: 8051 Embedded CRT Monitor Controller (Mask Version)
Company: Myson Technology
Datasheet: Download MTV112A16 datasheet File size : 119 kB
Request For quote: Find where to buy MTV112A16
Datasheet text preview:
MTV112A
8051 Embedded CRT Monitor Controller MASK Version
FEATURES
8051 core. 384-bytes internal RAM. 16K-bytes program Mask ROM. 14-channels 10V open-drain PWM DAC, 10 dedicated channels and 4 channels shared with I/O pin. 28 bi-direction I/O pin,12 dedicated pin,12 shared with DAC,4 shared with DDC/IIC interface. 5-output pin shared with H/V sync output and self test output pins. SYNC processor for composite separation, polarity and frequency check, and polarity adjustment. Built-in monitor self-test pattern generator. Built-in low power reset circuit. One slave mode IIC interface and one master mode IIC interface. IIC interface for DDC1/DDC2B and EEPROM; only one EEPROM needed to store DDC1/DDC2B and display mode information. Dual 4-bit ADC or 4 channel 6-bit ADC. Watchdog timer with programmable interval. 40-pin PDIP and 44-pin PLCC package.
GENERAL DESCRIPTION
The MTV112A micro-controller is an 8051 CPU core embedded device specially tailored to CRT monitor applications. It includes an 8051 CPU core, 384-byte SRAM, 14 built-in PWM DACs, DDC1/DDC2B interface, 24Cxx series EEPROM interface, A/D converter and a 16K-bytes internal program Mask ROM.
BLOCK DIAGRAM
STOUT P1.0-7 X1 P0.0-7 RD WR P0.0-7 RD WR
XFR
HSYNC
H / VSYNC CONTROL
VSYNC HBLANK VBLANK
X2
8051 CORE
INT 1 RST
WATCH-DOG TIMER
RST
P2.0-3 P3.0-P3.2
14 CHANNEL PWM DAC
DA0-9
DA10-13
P3.4 P2.4-7
ADC
AD0 AD1
HSCL HSDA
DDC 1/2 B & FIFO INTERFACE
ISCL
IIC INTERFACE
ISDA
USA: 4020 Moorpark Avenue Suite 115 No. 2, Industry East Rd. III, Science-Based Industrial Park, Hsin-Chu, Taiwan San Jose, CA, 95117 Tel: 408-243-8388 Fax: 408-243-3188 Tel: 886-3-5784866 Fax: 886-3-5784349
Myson Century, Inc. Taiwan:
sales@myson.com.tw www.myson.com.tw Rev. 2.0 August 2002 page 1 of 20
MTV112A
1.0 PIN CONNECTION
P1.0 P1.1/HALFV P1.2/HALFH P1.3/HCLAMP P1.4/AD2 P1.5/AD3 P1.6/AD0 P1.7/AD1 RST HSCL/P3.0/Rxd HSDA/P3.1/Txd ISDA/P3.2/INT0 HSYNC ISCL/P3.4/T0 VSYNC HBLANK/P4.1 VBLANK/P4.0 X2 X1 VSS VDD DA0/P5.0 DA1/P5.1 DA2/P5.2 DA3/P5.3 DA4/P5.4 DA5/P5.5 DA6/P5.6 DA7/P5.7 DA8 DA9 STOUT/P4.2 DA10/P2.7 DA11/P2.6 DA12/P2.5 DA13/P2.4 P2.3 P2.2 P2.1 P2.0/INT0
P1.0 P1.1/HALFV P1.2/HALFH P1.3/HCLAMP P1.4/AD2 P1.5/AD3 P1.6/AD0 P1.7/AD1 RST HSCL/P3.0/Rxd HSDA/P3.1/Txd ISDA/P3.2/INT0 HSYNC ISCL/P3.4/T0 VSYNC HCLAMP/P4.4 HBLANK/P4.1 VBLANK/P4.0 X2 X1 VSS
VDD DA0/P5.0 DA1/P5.1 DA2/P5.2 DA3/P5.3 DA4/P5.4 DA5/P5.5 DA6/P5.6 DA7/P5.7 DA8
MTV112A
MTV112A
DA9 HALFH/P4.3 STOUT/P4.2 DA10/P2.7 DA11/P2.6 DA12/P2.5 DA13/P2.4 P2.3 P2.2 P2.1 P2.0/INT0
P1.3/HCLAMP
P1.2/HALFH
P1.1/HALFV
P1.4/AD2
DA0/P5.0
DA1/P5.1
DA2/P5.2 42
DA3/P5.3 41
VDD
P1.0
44
43
NC P1.5/AD3 P1.6/AD0 P1.7/AD1 RESET HSCL/P3.0/Rxd HSDA/P3.1/Txd ISDA/P3.2/INT0 HSYNC ISCL/P3.4/T0 VSYNC
40 39 38 37 36 35
6
5
4
3
2
1
NC
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
DA4/P5.4 DA5/P5.5 DA6/P5.6 DA7/P5.7 DA8 DA9 STOUT/P4.2 DA10/P2.7 DA11/P2.6 DA12/P2.5 NC
MTV112A
34 33 32 31 30 29
VBLANK/P4.0
HBLANK/P4.1
DA13/P2.4
X2
X1
P2.1
P2.2
P2.0/INT0
P2.3
VSS
NC
Page 2 of 20
MTV112A
2.0 PIN DESCRIPTIONS
Name P1.0 P1.1/HALFV P1.2/HALFH P1.3/HCLAMP P1.4/AD2 P1.5/AD3 P1.6/AD0 P1.7/AD1 RST HSCL/P3.0/Rxd HSDA/P3.1/Txd ISDA/P3.2/INT0 HSYNC ISCL/P3.4/T0 VSYNC HCLAMP/P4.4 HBLANK/P4.1 VBLANK/P4.0 X2 X1 VSS P2.0/INT0 P2.1 P2.2 P2.3 DA13/P2.4 DA12/P2.5 DA11/P2.6 DA10/P2.7 STOUT/P4.2 HALFH/P4.3 DA9 DA8 DA7/P5.7 DA6/P5.6 DA5/P5.5 DA4/P5.4 DA3/P5.3 DA2/P5.2 DA1/P5.1 DA0/P5.0 VDD Type I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I I/O I O O O O I I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin# 42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 44 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 27 28 30 31 32 33 34 35 36 37 38 39 41 42 43 44 1 Description General purpose I/O General purpose I/O / Vsync half frequency output. General purpose I/O / Hsync half frequency output. General purpose I/O / Hsync clamp pulse output. General purpose I/O / ADC input. General purpose I/O / ADC input. General purpose I/O / ADC input General purpose I/O / ADC input Active high reset IIC clock / General purpose I/O / Rxd IIC data / General purpose I/O / Txd IIC data / General purpose I/O / INT0 Horizontal SYNC or Composite SYNC IIC clock / General purpose I/O / T0 Vertical SYNC Hsync clamp pulse output / General purpose output Horizontal blank / General purpose output Vertical blank / General purpose output Oscillator output Oscillator input Ground General purpose I/O / INT0 General purpose I/O General purpose I/O General purpose I/O PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) Self-test video output / General purpose output Hsync half frequency output / General purpose output PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) PWM DAC output / General purpose I/O (open-drain) Positive power supply
3.0 FUNCTIONAL DESCRIPTION
Page 3 of 20
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