|
Details, datasheet, quote on part number:NHI-15102RT
| |
| Part: | NHI-15102RT |
| Category: | Communication => Others |
| Description: | Description = MIL-STD-1553, Dual Redundant, Remote Terminal, 4k Words Static RAM, Multichip, Monolithic Transceivers, Macair, With Separation of Broadcast Data Pointer Tables And External Time Tag Clock Input. ;; Power = +5V ;; Stub Coupled XFMR Ratio = 1.00:1.79 ;; Package Styles = 69PGA,68QFP ;; Desc SMD P/n = 5962-9168710 |
| Company: | National Hybrid (NHI) |
| Datasheet: | Download NHI-15102RT datasheet File size : 773 kB |
| Request For quote: | Find where to buy NHI-15102RT
|
| |
Datasheet text preview:
National Hybrid, Inc.
Mil-Std-1553/1760 Remote Terminal Products User's Manual
Version 3.2 April 1996
The information provided in this document is believed to be accurate; however, no responsibility is assumed by NATIONAL HYBRID, INC. for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice.
2200 SMITHTOWN AVENUE, RONKONKOMA, NY 11779 TELEPHONE (516) 981-2400 FAX 516-981-2445 Sales FAX 516-981-8888
Table of Contents
1.0 2.0 3.0 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.3.1 3.3.3.2 3.3.4 3.3.4.1 3.3.4.2 3.3.4.3 3.3.4.4 3.3.4.5 3.3.4.6 3.3.5 3.4 4.0 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.8.1 4.2.9 4.2.10 4.2.11 4.2.12 4.2.13 4.2.14 4.2.15 4.2.16 4.2.17 4.2.18 4.2.19 4.2.20 SCOPE APPLICABLE DOCUMENTS INTRODUCTION FEATURES BLOCK DIAGRAM PROTOCOL CHIP DESCRIPTION HOST BUS INTERFACE UNIT I/O BUS INTERFACE UNIT INTERRUPT CONTROL UNIT ICU REGISTERS ICU FIFO DUAL REDUNDANT 1553 FRONT END MANCHESTER DECODER MANCHESTER ENCODER GAP COUNTER NO RESPONSE COUNTER MINIMUM RESPONSE TIME COUNTER TIMEOUT COUNTER MESSAGE PROCESSOR UNIT HARDWIRE TERMINAL ADDRESS DATA STRUCTURE ADDRESS MAP INTERNAL REGISTERS CONTROL REGISTER POINTER TABLE ADDRESS REGISTER BASIC STATUS INTERRUPT REQUEST REGISTER INTERRUPT MASK REGISTER INTERRUPT VECTOR REGISTER AUXILIARY VECTOR REGISTER REAL TIME CLOCK REAL TIME CLOCK CONTROL REGISTER FIFO READ FIFO RESET LAST COMMAND LAST STATUS RESET REMOTE TERMINAL ENCODER STATUS CONDITION REGISTER ENCODER DATA REGISTER ENCODER DATA TRANSMIT REQUEST ENCODER COMMAND TRANSMIT REQUEST EXTERNAL TERMINAL ADDRESS BUFFER COMMAND OUTPUT PINS 4 4 4 4 5 7 7 7 7 8 9 9 9 10 10 10 10 10 10 11 12 12 13 13 15 15 16 16 16 16 17 17 19 19 19 19 19 19 20 20 20 21 21 21
-1-
4.2.21 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.4.1 4.3.4.2 4.3.4.3 5.0 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 5.2.10 5.2.11 5.2.12 5.2.13 5.2.14 5.2.15 5.2.16 5.2.17 5.2.18 6.0 6.1 6.2 7.0 7.1 7.2 8.0 8.1 8.2 8.3 8.4 9.0 9.1 9.2 9.3 9.4 9.5
I/O TAG REGISTER DATA TABLES MESSAGE ILLEGALITY DATA TABLE TAG WORD DATA TABLE POINTER DATA TABLE BUFFERING SCHEME RT RAM ACCESS HOST RAM ACCESS READ MODIFY WRITE RAM ACCESS MODE CODE OPERATION GENERAL TABLE OF MODE CODE RESPONSES DYNAMIC BUS CONTROL SYNCHRONIZE WITHOUT DATA TRANSMIT LAST STATUS WORD INITIATE SELF TEST TRANSMITTER SHUTDOWN OVERRIDE TRANSMITTER SHUTDOWN INHIBIT TERMINAL FLAG OVERRIDE INHIBIT TERMINAL FLAG RESET REMOTE TERMINAL RESERVED MODE CODES TRANSMIT VECTOR WORD SYNCHRONIZE WITH DATA TRANSMIT LAST COMMAND TRANSMIT BIT WORD SELECTED TRANSMITTER SHUTDOWN OVERRIDE SELECTED TRANSMITTER SHUTDOWN RESERVED MODE CODES RESERVED MODE CODES NHI-RT INITIALIZATION NHI-RT INTERNAL INITIALIZATION HOST INITIALIZATION OF NHI-RT INTERRUPT HANDLING HARDWARE INTERRUPT ACKNOWLEDGE SOFTWARE INTERRUPT ACKNOWLEDGE PIN FUNCTIONAL DESCRIPTION GENERAL PURPOSE SIGNALS HOST INTERFACE SIGNALS I/O BUS INTERFACE SIGNALS MIL-STD-1553B INTERFACE SIGNALS PIN FUNCTIONS AND MECHANICAL DRAWINGS NHI-1553RT NHI-1553RTFP NHI-1554RT NHI-1554RTFP NHI-1561RT/NHI-1591RT
22 22 22 23 24 24 24 25 25 25 25 26 26 26 26 27 27 27 28 28 28 29 29 30 30 31 31 31 31 32 32 33 33 34 35 35 35 35 35 36 37 38 39 40 41 42 43
-2-
|
|
