· Advanced programmable PLL design Very low Jitter and Phase Noise 40ps Pk-Pk typical) Output frequency to 375MHz CMOS. Supports differential CMOS output to produce PECL, LVDS inputs. Crystal inputs: o Fundamental crystal: 3 RD overtone crystal: 75MHz o Reference input: to 200MHz Accepts <1.0V reference signal input voltage One programmable I/O pin can be configured as Output Enable (OE), or Frequency Selection input (FSEL), or Reference clock. Single ± 10% power supply Operating temperature range from ° C Available in 8-pin MSOP/SOIC, 6-pin SOT Green/ RoHS compliant packages.
The is a low-cost general purpose frequency synthesizer and a member of PhaseLink's Factory Programmable `Quick Turn Clock (QTC)' family. PhaseLink's PL611-30 product family can generate any output frequency to 375 MHz from fundamental crystal input between 10 MHz - 30 MHz, a 3rd overtone crystal to 75Mhz. The PL611-30 produces differential CMOS outputs to support PECL, LVDS, and CMOS inputs.
Xtal OSC FRef. R- counter Phase Detector M-counter ( 6 -bit) Charge Pump Loop Filter
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 1
200ppm One output pin can be tuning. configured CLK2 = FIN FIN/2 2. FSEL - input OE - input
Crystal or Reference input pin GND connection Programmable Clock Output [note:CLK0=~CLK1] VDD connection Do No Connect This programmable I/O pin can be configured CLK2 ( FIN or FIN/2) output, or OE input, or Frequency Selection (FSEL) input pin. This pin has an internal 60K pull up resistor. State 0 1 (default) OE Tristate CLK[0:1] Normal mode FSEL Select Bank '0' ROM Select Bank `1' ROM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 2
Supply Voltage Range Input Voltage Range Output Voltage Range Data Retention º C Soldering Temperature Storage Temperature Ambient Operating Temperature* -65 -40
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
Fundamental Crystal 3 rd Overtone Crystal At power-up (after VDD increases over 1.62V) Frequency vs. VDD+/-10% 15pF Load, 10/90%VDD, Standard drive 15pF Load, 10/90%VDD, High drive 15pF Load, 90/10%VDD, Standard drive 15pF Load, 90/10%VDD, High drive At VDD/2 Equal loading (15 pF). Equal frequency & drive strength With capacitive decoupling between VDD and GND. Operating only one output.
Settling Time VDD Sensitivity Output Rise Time
Output Fall Time Duty Cycle Max. output skew between same frequency clocks Period Jitter, peak-to-peak* (measured from 10,000 samples)
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 3