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Details, datasheet, quote on part number: PLL130-07SI
 
 
Part numberPLL130-07SI
Category
DescriptionHigh Speed Translator Buffers: Single Ended to PECL or LVDS
CompanyPhaseLink (PLL)
DatasheetDownload PLL130-07SI datasheet
 


 
Specifications, Features, Applications

High Speed Translator Buffers: Single ended to PECL or LVDS FEATURES· Differential PECL (PLL130-68) or LVDS (PLL130-69) output. Accepts any single-ended REFIN input (with as low as 100mV swing). Internal AC coupling of REFIN Input range from to 1.0 GHz. No Vref required. No external current source required. to 3.3V operation. Available in 3x3mm QFN. PIN CONFIGURATION

DESCRIPTION The PLL130-68 and PLL130-69 are low cost, high performance, high speed, translator buffers that reproduce any input frequency from to 1.0GHz. They provide a pair of differential outputs (PECL for PLL130-68 or LVDS for PLL13069). Thanks to an internal AC coupling of the reference input (REFIN), any input signal with at least 100mV swing can be used as reference signal, regardless of its DC value. These chips are ideal for conversion from clipped sine wave, TTL, CMOS, or differential signal to LVDS or PECL.

OESEL 0 (Default) 1 OECTRL 0 (Default) 0 1 (Default) OUTPUT STATE Output enabled Tri-state Output enabled

OECTRL input: Logical states defined by PECL levels.

OESEL 0 (Default) 1 OECTRL 0 1 (Default) 0 (Default) 1 OUTPUT STATE Tri-state Output enabled Output enabled Tri-state

OECTRL input: Logical states defined by CMOS levels.

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1

High Speed Translator Buffers: Single ended to PECL or LVDS PIN DESCRIPTION
Description

Reference input signal. The frequency of this signal will be reproduced at the output (after translation to PECL or LVDS level). Output enable input (See OE Logic Table on page 1). Ground connector. Output enable logic selector (See OE Logic Table on page 1). Complementary output. PECL_bar on PLL130-68, LVDS_bar on PLL130-69. True output. PECL on PLL130-68, LVDS PLL130-69. 3.3V Power supply. Additional true output. PECL on PLL130-68, LVDS on PLL130-69. This output is the same as pin 11. Additional complementary output. PECL_bar on PLL130-68, LVDS_bar on PLL130-69. This output is the same as pin 10.

Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.

Supply Current (both outputs loaded) Operating Voltage Output Clock Duty Cycle Short Circuit Current

Fout = 156.25MHz, PECL Fout = 156.25MHz, LVDS @ Vdd ­ 1.3V (PECL) @ 1.25V (LVDS)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/29/04 Page 2

High Speed Translator Buffers: Single ended to PECL or LVDS
Input Frequency Input signal swing Output Frequency
Clock Rise Time Clock Fall Time

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/29/04 Page 3




Related products with the same datasheet
PLL130-05QC-R   PLL130-05QI   PLL130-05SC   PLL130-05SI   PLL130-07QC   PLL130-07QC-R  
PLL130-07QI   PLL130-07SC   PLL130-07SC-R   PLL130-08QC   PLL130-08QC-R  


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