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Details, datasheet, quote on part number:PJ324
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Datasheet text preview:
PJ324 Quad Low Power Operational Amplifiers
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he PJ324 series are low-cost , quad operational amplifiers with true differential inputs. These have several distinct advantage over standard operational amplifier types in single supply applications. The quad amplifiers can operate at supply voltages as low as 3.0V or as high as 32V with very low
quiescent currents and eliminat the necessity for external biasing components in many applications. The output voltage range also includes the negative power supply voltage.
DIP -1 4 SOP -1 4
FEATURES
Short circuited protected outputs True differential input stage Single supply operation:3.0V to 32V Low input bias currents:100nA Max Four amplifiers per package Internally compensated Common mode range extends to negative supply Industry standard pinouts ESD clamps on the inputs increase raggedness without affecting device operation
P in: 1.Output 1 2.Input 1 (-) 3.Input 1(+) 4.Vcc 5.Input 2(+) 6.Input 2 (-) 7.Output 2 8.Output 3 9.Input 3 (-) 10.Input 3 (+) 11.Vee Gnd 12.Input 4 (+) 13.Input 4 (-) 14.Output 4
ORDERING INFORMATION
Device PJ324CD PJ324CS Operating Temperature -20 to +85 Package DIP-14 SOP-14
MAXIMUM RATING(Ta=+25,unless otherwise noted.)
Rating Power Supply Voltage Single Supply Split Supplies Input Differential Voltage Range (1) Input Common Mode Voltage Range Output Short Circuit Duration Junction Temperature Plastic Packages Storage Temperature Ceramic Package Plastic Packages NOTE : 1. Split Power Supplies. Symbol VCC VCC, VE E VIDR VICR tSC TJ 150 T st g - 65 to + 150 PJ324 ±16 Unit Vdc
32 -0.3 to 32 Continuous
Vdc Vdc
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2002/01 VER.A
PJ324 Quad Low Power Operational Amplifiers
ELECTRICAL CHARACTERISTICS (VCC= 5.0V, VE E =G ND, TA= 25 unle s s othe rwi s e note d.)
Max Unit Input Offset Voltage mV VCC= 5. 0V to 30V VICR= 0 V to VCC-0. 7V, Vo=1.4V, Rs=0 T A= 25 2.0 7.0 T A= T hi gh to T l ow (Note 1) 9.0 Average Temperature Coefficient of Input Offset Voltage VIO /T 7.0 V/ T A= T hi ge to T l ow (Note 1) Input Offset Current IIO 5.0 50 nA T A= T hi ge to T l ow (Note 1) 150 Average Temperature Coefficient of Input Offset Current IIO /T 10 pA/ T A= T hi ge to T l ow (Note 1) Input Bias Current IIB -90 -250 nA T A= T hi ge to T l ow (Note 1) -500 Input Common Mode Voltage Range (Note 2) V VICR VCC= 30V 0 28.3 VCC= 30V, T A= T hi ge to T l ow 0 28 Differential Input Voltage Range VIDR VCC V Large Signal Open-Loop Voltage Gain AVOL V/mV R L = 2. 0K, VCC= 15V, for Large Vo Swing 25 100 T A= T hi ge to T l ow (Note 1) 15 Channel Separation CS -120 dB 10KHzf20KHz, Input Referenced Common Mode Rejection CMR 65 70 dB Rs10K Power Supply Rejection PSR 65 100 dB Output Voltage - High Limit ( T A= T hi ge to T l ow ) (Note 1) VOH V VCC= 5. 0V, R L = 10K, T A= 25 3.3 3.5 VCC= 30V, R L = 2. 0K 26 VCC= 30V, R L = 10K 27 28 Output Voltage-Low Limit VOL 5.0 20 mV VCC= 5. 0V, R L = 10K, T A= T hi ge to T l ow (Note 1) Output Source Current (VID= + 1. 0V, VCC= 15V) IO+ mA T A= 25 20 40 T A= T hi ge to T l ow (Note 1) 10 20 Output Sink Current Io mA (VID= -1.0V, VCC= 15V) T A= 25 10 20 T A= T hi ge to T l ow (Note 1) 5.0 8.0 (VID= -1.0V, VCC= 200mV, T A= 25) 12 50 A Output Short Circuit Ground (Note 2) Isc 40 60 mA Power Supply Current (T A= T hi ge to T l ow ) (Note 1) Icc mA VCC= 30V (26V for LM2902), Vo=0V, R L = 3.0 VCC= 5. 0V, Vo=0V, R L = 1.2 Note: 1. Short circuits from the output to Vcc can cause excessive heating and eventual destruction . Destructive dissipation can result from simultaneous shorts on all amplifiers. 2. The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V The upper end of the common mode voltage range is Vcc-1.7V. Characteristics Symbol VIO Min PJ324 Typ
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2002/01 VER.A
PJ324 Quad Low Power Operational Amplifiers
Re pre s e n t a t i ve Circuit Sche m a t i c (O n e - Fo u rt h of Circuit Shown)
CIRCUIT DESCRIPTION T h e PJ324 series is made using four internally compensated, two-stage operational amplifiers. T h e first stage of each consists of differential input devices Q20 and Q18 with input buffer transistors Q21 and Q17 and the differential to single ended converter Q3 and Q4 . T h e first stage performs not only the first stage gain function but also performs the level shifting and transconductance reduction functions. By reducing the transconductance a smaller compensation capacitor (only 5.0pF ) can be employed , thus saving chip area. T h e transconductance reduction is accomplished by splitting the collectors of Q20 and Q18 . Another feature of this input stage is that the input common mode range can include the negative supply or ground, in single supply operation without saturating either the input devices or the differential to single-ended converter . T h e second stage consists of a standed current source load amplifier stage.
µ
Large Signal Voltage Followe r Re s po n s e Each amplifier is biased from an internal voltage regulator which has a low temperature coefficient thus giving each amplifier good temperature characteristics as will as excellent power supply rejection.
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2002/01 VER.A
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