|
|
Part: SB301
Category:
Communication
-> Network
-> Ethernet/DS1/E1 (T1/E1)
-> Gigabit Ethernet
Description: 1.25 Gigabit/s Ethernet Transceiver
Company: Silicon Bridge
Datasheet: Download SB301 datasheet File size : 331 kB
Request For quote: Find where to buy SB301
Datasheet text preview:
SB301 SB301
PRODUCT BRIEF
1.25 GIGABIT/S GIGABIT ETHERNET TRANSCEIVER
SB301 FEATURES § § § § § § § Up to 1.25 Gb/s CMOS Gigabit Ethernet Transceiver 10 bit parallel LVTTL/CMOS compatible digital interface Full duplex operation at 1.25 Gbps On chip phase locked loop (PLL) clock synthesis with 125 MHz reference clock Automatic lock to reference and user forced to lock to reference function COMMA detection and word alignment 64 pin TQFP package (10mm x 10mm or 14mm x 14mm) § § § § § § SB301 BENEFITS Low power (maximum total power consumption 290 mW at 1.25 Gbps) Low jitter receiver with integrated equalization for fibre or copper application Transmit jitter under 4ps RMS Low cost 0.35µm digital CMOS process operating at 3.3V On chip termination (50 ) or external termination, AC or DC coupling Built-in self test (BIST) allows for easy system level verification of the transceiver at maximum data rates
TX[9:0]
Data Capture
Serializer
Transmit Driver Termination
TXP,N
Transmit PLL REFCLK BIST Receive PLL Termination
RBC[1:0] Word Align
RX[9:0] COMDET
Clock/Data Recovery
Equalizer & Buffer
RXP,N
Sept 2000
1
SB301 SB301
PRODUCT BRIEF
SB301 is a programmable, high-performance transceiver for full duplex operations at 1.25 gigabits per second for Gigabit Ethernet. The chip includes receiver equalization circuitry to reduce inter-symbol interference (ISI) thus extending the range of communications at these high bit rates. The transmitter has a ten bit interface (TBI) for parallel LVTTL/CMOS data at 125 MHz reference clock. The transmit PLL clock is used by the serializer to send out data at 10x the parallel input rate. Internal termination which can be either 50 eliminates the need for any external termination at the serializer outputs, but user has option to terminate externally as well (with either 50 or 75 terminations). The synchronizer PLL and clock/data recovery circuit is used to lock to the input high-speed serial input bit stream. The recovered data is then passed on to the word align/comma detect circuitry for word alignment after which it is clocked out at the parallel ten bit interface. The recovered byte clocks, comma detect signal and transition detect signals are also made available to the system. A built-in self test (BIST) is available that can be used to do self test of the chip without the need for external digital parallel data. SB301 is manufactured using 0.35 µm standard low - cost single-poly digital CMOS process and operates with a single 3.3V supply. The chip is available in a 64 pin TQFP package in either a 10mm x 10mm or 14mm x 14mm form factor.
For more information on this product and other Silicon Bridge products, please contact us at Voice: 510.739.1224, Facsimile: 510.739.1212 or email: info@siliconbridge.com SILICON BRIDGE, Inc. 39500 Stevenson Place Suite 201, Fremont, CA 94539 http://www.siliconbridge.com
© 2000 Silicon Bridge, Inc. All Rights Reserved.
Sept 2000
1
Others parts begin by sb
SB-1 SB-2 SB-3 SB-4 SB-5 SB-6 SB-7 SB-8 SB-9 SB-10 SB-11 SB-12 SB-13 SB-14
|
|
|
