Details, datasheet, quote on part number: STK6002
PartSTK6002
CategoryOptoelectronics => Drivers/Controllers => LCDs => LCD monitor
TitleLCD monitor
DescriptionHigh Speed ADC-100/140MHz
CompanySyntec Semiconductor
DatasheetDownload STK6002 datasheet
  

 

Features, Applications

FEATURES 140 MSPS Maximum Conversion Rate 500 MHz Analog Bandwidth 1.0 V Analog Input Range 400 ps p-p PLL Clock Jitter Power-Down Mode 3.3 V Power Supply 3.3 V Three-State CMOS Outputs Demultiplexed Output Ports Data Clock Output Provided Low Power: 570 mW Typical Internal PLL Generates CLOCK from HSYNC Serial Port Interface Fully Programmable Supports Alternate Pixel Sampling for HigherResolution Applications APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters GENERAL DESCRIPTION

8 CLAMP A/D 8 ROUTA ROUTB GOUTA GOUTB BOUTA BOUTB DATACK HSOUT 0.15V

The is a complete 8-bit 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full-power analog bandwidth of 500 MHz supports display resolutions × 1024 (SXGA) 75 Hz with sufficient input bandwidth to accurately acquire and digitize each pixel. To minimize system cost and power dissipation, the AD9884A includes an internal +1.25 V reference, PLL to generate a pixel clock from HSYNC, and programmable gain, offset and clamp circuits. The user provides only +3.3 V power supply, analog input, and HSYNC signals. Three-state CMOS outputs may be powered by a supply between 2.5 V and 3.3 V. The AD9884A's on-chip PLL generates a pixel clock from the HSYNC input. Pixel clock output frequencies range from

20 MHz to 140 MHz. PLL clock jitter is typically 400 ps p-p relative to the input reference. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A 32-step sampling phase adjustment is provided. Data, HSYNC and Data Clock output phase relationships are always maintained. The PLL can be disabled and an external clock input provided as the pixel clock. A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. This device is fully programmable via a two-wire serial port. Fabricated in an advanced CMOS process, the AD9884A is provided in a space-saving 128-lead MQFP surface mount plastic package and is specified over +70° C temperature range.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000

AD9884A­SPECIFICATIONS Clock Frequency = Maximum, Control Registers Programmed to Default State)

Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes ANALOG INPUT Input Voltage Range Minimum Maximum Gain Tempco Input Bias Current Input Offset Voltage Input Full-Scale Matching Offset Adjustment Range REFERENCE OUTPUT Output Voltage Temperature Coefficient SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Data to Clock Skew, tSKEW tBUFF tSTAH tDHO tDAL tDAH tDSU tSTASU tSTOSU HSYNC Input Frequency Maximum PLL Clock Rate Minimum PLL Clock Rate PLL Jitter Sampling Phase Tempco DIGITAL INPUTS Input Voltage, High (VIH) Input Voltage, Low (VIL) Input Current, High (IIH) Input Current, Low (IIL) Input Capacitance DIGITAL OUTPUTS Output Voltage, High (VOH) Output Voltage, Low (VOL) Duty Cycle DATACK, DATACK Output Coding +25°C Full +25°C Full I VI Temp Test Level AD9884AKS-100 Min Typ Max Guaranteed AD9884AKS-140 Min Typ Max Guaranteed Unit Bits LSB

Parameter POWER SUPPLY VD Supply Voltage VDD Supply Voltage PVD Supply Voltage ID Supply Current (VD) IDD Supply Current (VDD)3 IPVD Supply Current (PVD) Total Power Dissipation Power-Down Supply Current Power-Down Dissipation DYNAMIC PERFORMANCE Analog Bandwidth, Full Power Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR)4 (Without Harmonics) fIN = 40.7 MHz Crosstalk THERMAL CHARACTERISTICS JC­Junction-to-Case Thermal Resistance JA­Junction-to-Ambient Thermal Resistance Temp Full +25°C Full +25°C Full Test Level VI AD9884AKS-100 Min Typ Max AD9884AKS-140 Min Typ Max Unit mA mW MHz ns dB dBc

NOTES 1 VCORNGE = 01, CURRENT = 001, PLLDIV VCORNGE = 10, CURRENT = 110, PLLDIV DEMUX = 1; DATACK and DATACK load = 15 pF; Data load = 5 pF. 4 Using external pixel clock. Specifications subject to change without notice.

to +70°C MQFP to +70°C MQFP AD9884A/PCB +25°C Evaluation Board EXPLANATION OF TEST LEVELS Test Level I. 100% production tested. II. 100% production tested at +25°C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at +25°C; guaranteed by design and characterization testing.

VD, PVD. +4 V PVD to VD. 0.5 V VDD. +4 V Analog Inputs. ­0.5 V REFIN. 0.0 V Digital Inputs. 0.0 V Digital Output Current. 20 mA Operating Temperature. to +85°C Storage Temperature. to +150°C Maximum Junction Temperature. +175°C Maximum Case Temperature. +150°C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9884A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.


 

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