|Category||Communication => Telephony => Voice Processors|
|Description||60" Adpcm Voice Controller|
|Datasheet||Download STK88C2441 datasheet
* Operating voltage 5.5V. * Maximum CPU operating frequency 2.7V. * Provide X'tal or RC oscillator. Both can run at high speed or slow speed(low power). RC oscillator can detect internal or external resister automatically. * Support 4M bytes program and data ROM. 256K bytes of them are built-in. * Built in 128 bytes RAM. * I/O port. 24 I/O pins. of 24 pins with wake up function. * Six 8-bit timers. * Four channels for voice or melody processing. * Two DACs for voice or melody playing. Also, internal programming for single DAC playing. * One pair of PWM for voice or melody playing. * Eight interrupt sources : NMI - Can be Watchdog Timer interrupt IRQ0 - Timer 0 interrupt IRQ1 - Timer 1 interrupt IRQ2 - Timer 2 interrupt IRQ3 - Timer 3 interrupt IRQ4 - Timer 4 interrupt IRQ5 - External interrupt IRQ6 - Base Timer interrupt IRQ7 - Timer 5 interrupt
Pin Name A0-A13 D0-D7 CEB /EXTROM PWM1 PWM2 VCOCAP RXOSC XOSC2 XR RESB TESTB VDD VDD(PWM) GND GND(PWM) I/O O I/O
Function description 8-bit I/O pins for port 1 with wake-up interrupt I/O 8-bit I/O pins for port 2. 8-bit I/O pins for port 3. PC0-PC7 will changed to BANK0BANK7 output if bank number is less than or /DIROM=0. Address bus. Data bus. External ROM chip enable. =0 Disable internal ROM. =1 Enable internal ROM if bank number is greater than $EF. Current output port Current output port Voltage output port Voltage output port PLL used. X'TAL or Ring osc pad X'TAL pad Bias input for RC oscillator. System reset pin; internal pull_high. Test pin; internal pull_high. Power for PWM module Ground for PWM module
1) RAM 0000-007F for data storage. 0100-017F for stack and data area.. This area is overlapped with 0000-007F. 2) ROM Max. 4M bytes for program and speech data area. This area splits into 256 banks (0~255). There are 16k bytes for every bank. The last 16 banks (240-255) are built-in. If /DIROM=1 and bank number is greater than $EF, then internal ROM is read. /DIROM=0 or bank number is less than
$F0, then external ROM is read. Internal ROM related address shows below: BANK numberCPU address Internal ROM address bank 8000-BFFF 00000-03FFF bank 8000-BFFF 04000-07FFF bank 8000-BFFF 08000-0BFFF............................................................................... bank 8000-BFFF 3C000-3FFFF (bank 3C000-3FFFF) If RESET or IRQ or NMI or Bank address=FF, ROM address will indicate to 3C000-3FFFF. FFFF, FFFE - IRQ vector. FFFD, FFFC - RES vector. FFFB, FFFA - NMI vector for watchdog interrupt.
Clear timer 0 flag. Clear timer 1 flag. Clear timer 2 flag. Clear timer 3 flag. Clear timer 4 flag. Clear External flag. Clear Base Timer flag. Clear timer 5 flag..
|Some Part number from the same manufacture Syntec Semiconductor|
|STK88C4050 ROM-less Adpcm Voice Controller.|
|STK88C4831 12" Adpcm Voice Controller.|
5962-90854 : Hermetically Sealed, Transistor Output Optocouplers For Analog And Digital Applications.
77105 : 25.6 MBPS Atm PHY With TC & PMD. The is a member of IDT's family of products developed to support Asynchronous Transfer Mode (ATM) data communications and networking. The IDT77105 provides the Transmission Convergence (TC) and (PMD) layers a 25.6 Mbps ATM PHY suitable for ATM networks using Unshielded Twisted Pair (UTP) Category 3 (or better) wiring. The UTOPIA interface provides standardized.
A3123LT : Hall-effect Switches For High-temperature Operation. These Hall-effect switches are monolithic integrated circuits with tighter magnetic s, designed to operate continuously over extended temperatures to +150°C, and are more stable with both temperature and supply voltage changes. The unipolar switching characteristic makes these devices ideal for use with a simple bar or rod magnet. The three basic devices.
AT76C551 : Single-chip Bluetooth Controller. Implements BluetoothTM on Short Distance Wireless Communication in Provides 1 Mbps Aggregate Bit Rate Supports Frequency Hopping Spread Spectrum Physical-layer Interface to Dedicated Transceiver with Frequency Hopping Algorithm Implemented in Hardware Provides Baseband Functions in Hardware which Implement Bluetooth Low-level Bit Processing Such as Forward.
CDC2510C : 3.3v Phase-lock Loop Clock Driver. Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2 Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 125 MHz Static tPhase Error Distribution at 66 MHz to 100 MHz ±150 ps Drop-In Replacement for TI CDC2510A With Enhanced Performance Jitter (cyc cyc) at 66 MHz to 100 MHz is |100 ps| Available in Plastic 24-Pin TSSOP.
CMX654 : V.23 Transmit Modulator. 1200bits/sec, V23 Transmit Modulator to 5.5V Supply: 1mA typical at 3V Zero Power Mode: 1µA typical 1200bits/sec Tx Data Retiming 3.58MHz Xtal/Clock Rate Meets ITU and ETSI s 16 Pin SOIC and DIP Packages Applications Caller ID generation for: ISDN Terminal Adapters Wireless Local Loop System ISDN PABX Applications Pair-Gain Systems Public Switched Telephone.
ISL3692 : Dual Band Direct Conversion Transceiver. The Intersil is a highly integrated SiGe process, Dual Band direct conversion transceiver and is part a 2.4/5.2GHz, Worldwide IEEE802.11a/b/g compliant radio chipset. The ISL3692 directly interfaces with Intersil's ISL3886 Medium Access Controller with Integrated Baseband processor. The addition of Intersil's ISL3992 power amplifier and ISL3092 11GHz.
MTD655 : 5-Port 10M/100M Dual Speed Hub With Built-in 2-Port Switch. IEEE802.3 Clause 9 and IEEE802.3u Cluse 27 compliant. Provide 4 RMII (Reduced Media Independent Interface) ports and 1 MII port. Provide 2 inter_repeater stacking bus for 10M and 100M port expansion each. Support stacking to 4 units without any external arbitration logic ( if use external arbitration logic, theoretically can stack to 6 units and up).
PAC680GQT : P/active High Performance Gtl/ecl Local Termination Network.
PCD8582D-2 : 256 X 8-bit CMOS EePROMs With I2c-bus Interface. Product Supersedes data of February 1992 File under Integrated Circuits, IC12 December 1994 Low power CMOS maximum active current mA maximum standby current 10 µA (at 6.0 V), typical 4 µA Non-volatile storage of 2-Kbits organized × 8-bits Single supply with full operation down 2.5 V On-chip voltage multiplier Serial input/output Write operations.
S3457 : OC-48 Sonet/sdh/atm 4-Bit Transceiver. SiGe BiCMOS Technology Complies with Bellcore and ITU-T s 4-bit LVDS data path at 622.08 Mbps On-chip, high-frequency PLL for clock generation Supports OC-48 (2.488 Gbps) Reference frequency of 155.52 MHz Diagnostic loopback mode Supports line timing Lock detect Signal detect input Low jitter LVDS interface Internal FIFO to decouple transmit clocks.
STV2110A : Pal-secam Luma-chroma & Deflection Processor. RGB AND FAST BLANKING INPUTS AUTOMATIC CUT-OFF CONTROL DC-CONTROLLED BRIGHTNESS, CONTRAST AND SATURATION CERAMIC 500kHz VCO FOR LINE DEFLECTION CHROMA STANDARD AUTOMATIC IDENTIFICATION BIDIRECTIONAL I/O FOR CHROMA STANDARD PHASE-LOCKED REFERENCE OSCILLATOR USING A STANDARD 4.43MHz OSD CAPABILITY ON OUTPUTS VIDEO IDENTIFICATION GENERATOR Used with the TDA8222,.
TAPC640L3X : Atlanta Atm Lite Port Controller (APC Lite). TAPC640L3x ATLANTA ATM Lite Port Controller (APC Lite) The Agere Systems ATM Lite Port Controller (APC) IC is part of the ATLANTA chip set that provides a highly integrated, innovative, and complete VLSI solution for implementing the ATM layer of an ATM switch system. The ATLANTA chip set allows for highperformance, feature-rich, and cost-effective.
PAS5351 : The PAS5351 and the PAS5361 create a Gigabit Ethernet PON Optical Line Terminal (OLT) optical burst receiver dedicated for use in Gigabit Ethernet Passive Optical Network (IEEE 802.3ah EPON) transceivers. The PAS5351 provides the burst-mode Trans-Impedance Amplifier (TIA) function and the PAS5361 provides the burst-mode Limiting Amplifier (LIA) function.