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Details, datasheet, quote on part number:HDMP-1014
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Datasheet text preview:
Low Cost Gigabit Rate Transmit/Receive Chip Set Technical Data
HDMP-1012 Transmitter HDMP-1014 Receiver
Features · Transparent, Extended · · · · ·
Ribbon Cable Replacement Implemented in a Low Cost Aluminum M-Quad 80 Package High-Speed Serial Rate 1501500 MBaud Standard 100K ECL Interface 16, 17, 20, or 21 Bits Wide Reliable Monolithic Silicon Bipolar Implementation On-chip Phase-Locked Loops - Transmit Clock Generation - Receive Clock Extraction
Description
The HDMP-1012 transmitter and the HDMP-1014 receiver are used to build a high speed data link for point to point communication. The monolithic silicon bipolar transmitter chip and receiver chip are each provided in a standard aluminum M-Quad 80 package. From the user's viewpoint, these products can be thought of as providing a "virtual ribbon cable" interface for the transmission of data. Parallel data loaded into the Tx (transmitter) chip is delivered to the Rx (receiver) chip over a serial channel, which can be either a coaxial copper cable or optical link. The chip set hides from the user all the complexity of encoding, multiplexing, clock extraction, demultiplexing and decoding. Unlike other links, the phaselocked-loop clock extraction circuit also transparently provides for frame synchronization - the user is not troubled with the periodic insertion of frame synchronization words. In addition, the dc balance of the line code is automatically maintained by the chip set. Thus, the user can transmit arbitrary data without restriction. The Rx chip also includes a state-machine
controller (SMC) that provides a startup handshake protocol for the duplex link configuration. The serial data rate of the T/R link is selectable in four ranges (see tables on page 5), and extends from 120 Mbits/s up to 1.25 Gbits/s. The parallel data interface is 16 or 20 bit single-ended ECL, pin selectable. A flag bit is available and can be used as an extra 17th or 21st bit under the user's control. The flag bit can also be used as an even or odd frame indicator for dual-frame transmission. If not used, the link performs expanded error detection. The serial link is synchronous, and both frame synchronization
Applications · Backplane/Bus Extender · Video, Image Acquisition · Point to Point Data Links · Implement SCI-FI Standard · Implement Serial HIPPI
Specification
5962-0049E (6/94)
573
and bit synchronization are maintained. When data is not available to send, the link maintains synchronization by transmitting fill frames. Two (training) fill frames are reserved for handshaking during link startup. User control space is also supported. If Control Available is asserted at the Tx chip, the least significant 14 or 18 bits of the data are sent and the Rx Control Available line will indicate the data as a Control Word. It is the intention of this data sheet to provide the design engineer all of the information regarding the HDMP-1012/1014 chipset necessary to design this product into their application. To assist you in using this data sheet, the following Table of Contents is provided.
Table of Contents
Topic Page Typical Applications ..... 575 Setting the Operating Rate .....576 Transmitter Block Diagram ....578 Receiver Block Diagram ........ 580 Transmitter Timing Characteristics ...... 582 Receiver Timing Characteristics ..... 583 DC Electrical Specifications .. 584 AC Electrical Specifications ... 584 Typical Lock-Up Times .......... 584 Absolute Maximum Ratings ... 585 Thermal Characteristics ........ 585 I/O Type Definitions ..... 585 Pin-Out Diagrams ........ 586 Transmitter Pin Definitions ... 587 Receiver Pin Definitions ........ 591 Mechanical Dimensions and Surface Mount Assembly Instructions ........ 595 Appendix I: Additional Internal Architecture Information ........596 Line Code Description ........... 596 Data Frame Codes ....... 596 Control Frame Codes ............ 597 Fill Frame Codes .......... 598 Tx Operation Principles ........ 599 Tx Encoding .......... 599 Tx Phase Locked Loop ...........600 Rx Operation Principles ........ 601 Rx Encoding .. 601 HDMP-1014 (Rx) Phase Locked Loop ........... 601 HDMP-1014 (Rx) Decoding ...602 HDMP-1014 (Rx) Link Control State Machine Operation Principle ....... 603 The State Machine Handshake Protocol .........603 Appendix II: Link Configuration Examples ..... 605 Duplex/Simplex Configurations ...... 605 Full Duplex ....605 Simplex Method I: Simplex with Low Speed Return Path ...... 606 Simplex Method II: Simplex with Periodic Sync Pulse ...........607 Simplex Method III: Simplex with External Reference Oscillator ......607 Data Interface for Single/Double Frame Mode ........ 608 Single Frame Mode (MDFSEL=0) ........ 608 Double Frame Mode (MDFSEL=1) ...... 609 Supply Bypassing and Integrator Capacitor ... 610 Integrating Capacitor ....610 Power Supply Bypassing and Grounding ....... 610 Electrical Connections ........... 611 I-ECL and O-ECL .......... 611 High Speed Interface: I-H50 & O-BLL ...........612 TTL and Positive 5 V Operation ...... 613 Mode Options ......... 614
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Typical Applications
The HDMP-1012/1014 chipset was designed for ease of use and flexibility. This allows the customer to tailor the use of this product, through the configuration of the link, based on their specific system requirements and application needs. Typical applications range from backplane and bus extension to digital video transmission. Low latency bus extension of a 16 or 20 bit wide data bus may be achieved using the standard duplex configuration (see Figure 1d). In full duplex, the HDMP1012/1014 chipset handles all of the issues of link startup, maintenance, and simple error detection. If the bus width is 32 or 40 bits wide, the HDMP-1012/1014 chipset is capable of sending the large data frame as two separate frame segments, as shown in Figure 1b. In this mode, called Double Frame Mode, the FLAG bit is used by the transmitter and receiver to indicate the first or second frame segment. The HDMP-1012/1014 chipset in Double Frame Mode may also be configured in full duplex to achieve a 32/40 bit wide bus extension. For digital video transmission, simplex links are more common. The HDMP-1012/1014 chipset can transmit 16 to 21 bits of parallel data in standard or broadcast simplex mode. Additionally, 32 to 40 bit wide data can be transmitted over a single line (in Double Frame Mode) or two parallel lines, as in Figure 1c.
Tx CLK A) 16/20 BIT SIMPLEX TRANSMISSION Rx CLK
MUX CLK
Tx
Rx CLK
DEMUX
B) 32/40 BIT SIMPLEX TRANSMISSION
Tx CLK
Rx CLK
Tx CLK
Rx CLK
C) 32/40 BIT SIMPLEX TRANSMISSION WITH HIGH CLOCK RATES
Tx CLK
Rx CLK
Rx CLK
Tx CLK
D) 16/20 BIT DUPLEX TRANSMISSION
Tx CLK
Rx CLK
Rx CLK . . . . . . . . Rx CLK E) SIMPLEX BROADCAST TRANSMISSION
Figure 1. Various Configurations Using the HDMP-1012/1014.
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