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Part: M29F080A90M6
Category:
Description:
Company: SGS-Thomson (acquired by ST Microelectronics, Inc.)
Datasheet: Download M29F080A90M6 datasheet File size : 1053 kB
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Datasheet text preview:
M29F080A
8 Mbit (1Mb x8, Uniform Block) Single Supply Flash Memory
s
SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 70ns PROGRAMMING TIME 8µs by Byte typical
44
s s
s s
16 UNIFORM 64 Kbyte MEMORY BLOCKS PROGRAM/ER ASE CONTROLLER
1
Embedded Byte Program algorithm Embedded Multi-Block/Chip Erase algorithm Status Register Polling and Toggle Bits Ready/Busy Output Pin
s
TSOP40 (N) 10 x 20mm
SO44 (M)
ERASE SUSPEND and RESUME MODES Read and Program another Block during Erase Suspend Figure 1. Logic Diagram
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TEMPORARY BLOCK UNPROTECTION MODE LOW POWER CONSUMPTION Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION Defectivity below 1 ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: F1h
A0-A19 W E G RP M29F080A RB VCC
s
s
20
8 DQ0-DQ7
s
s
VSS
AI00501C
April 2000
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M29F080A
Figure 2. TSOP Connections Figure 3. SO Connections
NC RP A11 A10 A9 A8 A7 A6 A5 A4 NC NC A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 VSS VSS 1 2 3 4 5 6 7 8 9 10 11 M29F080A 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VCC E A12 A13 A14 A15 A16 A17 A18 A19 NC NC NC NC W G RB DQ7 DQ6 DQ5 DQ4 VCC
A19 A18 A17 A16 A15 A14 A13 A12 E VCC NC RP A11 A10 A9 A8 A7 A6 A5 A4
1
40
10 11
M29F080A
31 30
20
21
AI00520B
NC NC W G RB DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3
AI00521B
Table 1. Signal Names
A0-A19 DQ0-DQ7 E G W RP RB VCC VSS NC Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Supply Voltage Ground Not Connected Internally
SUMMARY DESCRIPTION The M29F080A is an 8 Mbit (1Mb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed us-
ing a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected in groups to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in a TSOP40 (10 x 20mm) and SO44 packages and it is supplied with all the bits erased (set to '1').
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M29F080A
Table 2. Absolute Maximum Ratings (1)
Symbol Parameter Ambient Operating Temperature (Temperature Range Option 1) TA Ambient Operating Temperature (Temperature Range Option 6) Ambient Operating Temperature (Temperature Range Option 3) TBIAS TSTG VIO (2) VCC VID Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Identification Voltage Value 0 to 70 40 to 85 40 to 125 50 to 125 65 to 150 0.6 to 6 0.6 to 6 0.6 to 13.5 Unit °C °C °C °C °C V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns during transitions.
Table 3. Uniform Block Addresses, M29F080A
# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Size (Kbytes) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range F0000h-FFFFFh 7 E0000h-EFFFFh D0000h-DFFFFh 6 C0000h-CFFFFh B0000h-BFFFFh 5 A0000h-AFFFFh 90000h-9FFFFh 4 80000h-8FFFFh 70000h-7FFFFh 3 60000h-6FFFFh 50000h-5FFFFh 2 40000h-4FFFFh 30000h-3FFFFh 1 20000h-2FFFFh 10000h-1FFFFh 0 00000h-0FFFFh Protection Group
SIGNA L DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V IH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface. Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been protected.
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