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Part: HYB39S256400T-8
Category:
Memory
-> DRAM
Description: 256 Mbit Synchronous DRAM
Company: Siemens (acquired by Infineon Technologies Corporation)
Datasheet: Download HYB39S256400T-8 datasheet File size : 782 kB
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Datasheet text preview:
256 MBit Synchronous DRAM
HYB 39S256400/800/160T
Preliminary Information
· High Performance: -8 -8B 100 10 6 12 7 -10 100 10 7 15 8 Units MHz ns ns ns ns · Multiple Burst Read with Single Write Operation · Automatic and Controlled Precharge Command · Data Mask for Read/Write control (× 4, × 8) · Data Mask for byte control (× 16) · Auto Refresh (CBR) and Self Refresh · Suspend Mode and Power Down Mode · 8192 refresh cycles/64 ms 7,8 µ · Random Column Address every CLK (1-N Rule) · Single 3.3 V ± 0.3 V Power Supply · LVTTL Interface versions · Plastic Packages: P-TSOPII-54 400mil width (× 4, × 8, × 16) · -8 part for PC100 2-2-2 operation -8B part for PC100 3-2-3 operation -10 part for PC66 2-2-2 operation
fCK tCK3 tAC3 tCK2 tAC2
125 8 6 10 6
· Fully Synchronous to Positive Clock Edge · 0 to 70 °C operating temperature · Four Banks controlled by BA0 & BA1 · Programmable CAS Latency: 2, 3, 4 · Programmable Wrap Sequence: Sequential or Interleave · Programmable Burst Length: 1, 2, 4, 8
The HYB 39S256400/800/160T are four bank Synchronous DRAM's organized as 4 banks × 16 MBit × 4, 4 banks × 8 MBit × 8 and 4 banks × 4 MBit × 16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS' advanced 256 MBit DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3 V ± 0.3 V power supply and are available in TSOPII packages.
Semiconductor Group
1
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
Ordering Information Type LVTTL-Version HYB 39S256400T-8 on request P-TSOP-54-2 400 mil 125 MHz 4B × 16 M × 4 SDRAM PC100-222-620 P-TSOP-54-2 400 mil 100 MHz 4B × 16 M × 4 SDRAM PC100-323-620 P-TSOP-54-2 400 mil 66 MHz 4B × 16 M × 4 SDRAM PC66-222-820 P-TSOP-54-2 400 mil 125 MHz 4B × 8 M × 8 SDRAM PC100-222-620 P-TSOP-54-2 400 mil 100 MHz 4B × 8 M × 8 SDRAM PC100-323-620 P-TSOP-54-2 400 mil 66 MHz 4B × 8 M × 8 SDRAM PC66-222-820 P-TSOP-54-2 400 mil 125 MHz 4B × 4 M × 16 SDRAM PC100-222-620 P-TSOP-54-2 400 mil 100 MHz 4B × 4 M × 16 SDRAM PC100-323-620 P-TSOP-54-2 400 mil 66 MHz 4B × 4 M × 16 SDRAM PC66-222-820 Ordering Code Package Description
HYB 39S256400T-8B on request HYB 39S256400T-10 on request HYB 39S256800T-8 on request
HYB 39S256800T-8B on request HYB 39S256800T-10 on request HYB 39S256800T-8 on request
HYB 39S256800T-8B on request HYB 39S256800T-10 on request
Pin Description and Pinouts CLK CKE CS RAS CAS WE A0 - A12 BA0, BA1 Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select DQ Data Input/Output Power (+ 3.3 V) Ground Power for DQ's (+ 3.3 V) Ground for DQ's Not Connected
DQM, LDQM, UDQM Data Mask
VDD VSS VDDQ VSSQ
NC
Semiconductor Group
2
1998-10-01
HYB 39S256400/800/160T 256 MBit Synchronous DRAM
TSOPII-54 (10.16 mm × 22.22 mm, 0.8 mm pitch)
0.1±0.05
1±0.05
15°±5°
10.16 ±0.13 2)
0.8 15°±5° 0.35 +00..015 3)
0.15 +00..0036 -
0.5 ±0.1 11.76 ±0.2
26x 0.8 = 20.8
0.1 54x 0.2 M 54x
54
28
6 max
1 2.5 max 22.22 ±0.13 1) Index Marking
1) 2)
27
GPX09039
Does not include plastic or metal protrusion of 0.15 max per side Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side
Pin Configuration for × 4, × 8 & × 16 organized 256 M-DRAMs
Semiconductor Group
3
1998-10-01
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