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Part: TSC80C51-25IAB/883
Category:
Microcontrollers
Description: CMOS 0 to 44 MHZ Single-chip 8 Bit Microcontroller
Company: Temic Semiconductors (acquired by ATMEL Corporation)
Datasheet: Download TSC80C51-25IAB/883 datasheet File size : 174 kB
Request For quote: Find where to buy TSC80C51-25IAB/883
Datasheet text preview:
TSC80C31/80C51
CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller
Description
The TSC80C31/80C51 is high performance SCMOS versions of the 8051 NMOS single chip 8 bit µC. The fully static design of the TSC80C31/80C51 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TSC80C31/80C51 retains all the features of the 8051 : 4 K bytes of ROM ; 128 bytes of RAM ; 32 I/O lines ; two 16 bit timers ; a 5-source, 2-level interrupt structure ; a full duplex serial port ; and on-chip oscillator and clock circuits. In addition, the TSC80C31/80C51 has two software-selectable modes of reduced activity for further reduction in power consumption. In the Idle Mode the CPU is frozen while the RAM, the timers, the serial port, and the interrupt system continue to function. In the Power Down Mode the RAM is saved and all other functions are inoperative. The TSC80C31/80C51 is manufactured using SCMOS process which allows them to run from 0 up to 44 MHz with VCC = 5 V. The TSC80C31/80C51 is also available at 20 MHz with 2.7 V < Vcc < 5.5 V.
D TSC80C31/80C51-L16 : Low power version Vcc : 2.75.5 V Freq : 016 MHz D TSC80C31/80C51-L20 : Low power version Vcc : 2.75.5 V Freq : 020 MHz D TSC80C31/80C51-12 : 0 to 12 MHz D TSC80C31/80C51-20 : 0 to 20 MHz D TSC80C31/80C51-25 : 0 to 25 MHz
D D D D
TSC80C31/80C51-30 : 0 to 30 MHz TSC80C31/80C51-36 : 0 to 36 MHz TSC80C31/80C51-40 : 0 to 40 MHz TSC80C31/80C51-44 : 0 to 44 MHz*
* Commercial and Industrial temperature range only. For other speed and range please consult your sale office.
Features
D D D D D D D Power control modes 128 bytes of RAM 4 K bytes of ROM (TSC80C31/80C51) 32 programmable I/O lines Two 16 bit timer/counter 64 K program memory space 64 K data memory space D D D D D D Fully static design 0.8 µm CMOS process Boolean processor 5 interrupt sources Programmable serial port Temperature range : commercial, industrial, automotive and military
Optional
D Secret ROM : Encryption D Secret TAG : Identification number
MATRA MHS Rev. E (14 Jan.97)
1
TSC80C31/80C51
Interface
Figure 1. Block Diagram
2
MATRA MHS Rev. E (14 Jan.97)
TSC80C31/80C51
Figure 2. Pin Configuration
P0.0/A0
P0.1/A1
P0.2/A2
P1.5 P1.6 P1.7 RST
P0.3/A3
VCC
P1.4
P1.3
P1.2
P1.1
P1.0
NC
P0.4/A4 P0.5/A5 P0.6/A6 P0.7/A7 EA
DIL40
RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5
PLCC44
NC ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13
P2.2/A10
P2.3/A11
P2.0/A8
WR/P3.6
P2.1/A9
P01/A1
P02/A2
P11
P14
P13
P12
P10
NC
P03/A3
P00/A0
VCC
P15 P16 P17 RST RxD/P30 NC TxD/P31 INT0/P32 INT1/P33 T0/P34 T1/P35
P04 /A4 P05 /A5 P06 /A6 P07 /A7 EA
PQFP44
NC ALE PSEN P27 /A15 P26 /A14 P25 /A13
WR/P36
RD/P37
P23 /A11
P20 /A8
P21 /A9
P22 /A10
Diagrams are for reference only. Packages sizes are not to scale.
P24 /A12
XTAL2
XTAL1
V SS
NC
P2.4/A12
XTAL2
RD/P3.7
XTAL1
VSS
NC
MATRA MHS Rev. E (14 Jan.97)
3
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