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Part: ACE9050
Category:
Description: System Controller And Data Modem Advance Information
Company: Mitel Networks Corporation
Datasheet: Download ACE9050 datasheet File size : 484 kB
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ACE9050
System Controller and Data Modem Advance Information
Supersedes January edition, DS4290 - 2.3 DS4290 - 3.0 December 1997
The ACE9050 provides the control and interface functions needed for AMPS or TACS analog cellular handsets. The device has been designed using Mitel Semiconductor submicron CMOS technology for low power and high performance. The ACE9050 contains an embedded microcontroller and peripheral functions. The controller is of the 6303 type with a Serial Communication Interface, Timer, ROM and RAM. The peripheral functions are: Data Modem, SAT Management, Serial Chip Interfaces, I 2C Interface, two Pulse Width Modulators, IFC Counter, Tone generator, I/O ports, Watchdog and Crystal Oscillator. Several power down modes are incorporated in the device as is a processor emulation mode for software and system development. An index to this data sheet is given on pages 49 and 50.
FEATURES s Low Power, Low Voltage (3·6 to 5·0 V) Operation s 3·0V Memory Interface s Power Down and Emulation Modes s 6303R-type Microcontroller s AMPS or TACS Modem s Watchdog and Power Control Logic s SAT Detection, Generation and Loopback s 6K bytes RAM s Interface to FLASH and EEPROM Memories s 512 byte ROM Boot Block s I/O Ports for Keyboard Scanning s I2C Controller s Small Outline 100-pin package APPLICATIONS s AMPS and ETACS Cellular Telephones s Two-way Radio Systems RELATED PRODUCTS
The ACE9050 is part of Mitel Semiconductor's ACE chipset, together with the following: ACE9020 Receiver and Transmitter interface ACE9030 Radio Interface and Twin Synthesiser ACE9040 Audio Processor
OUTP2 [6] ICN LATCH1 OUTP2 [7] LATCH0 PWM2 DTFG EMUL IRQN POFFN VSS VSS VDD EXRESN C1008 MRN A15 A14 CPUCL R/W BAR DTMS PWM1 ECLK RXCD
75 76
LATC H3 SERV SYNTHCLK SYNTHDATA INRQ0 INRQ1 KPI [3] KPI [2] KPI [1] KPI [0] VDD VDD TXDATA TXSAT TXPOW AFC/RXDATA KPO [4] KPO [3] KPO [2] KPO [1] KPO [0] INP1[4] INP1[3] INP1[2] RXSAT
51 50
ACE9050
100 1
26 25
BA17 BA16 BA15 BA14 A13 A12 A11 A10 A9 A8 A7 A6 VDDM VSS VSS A5 A4 A3 A2 A1 A0 CSE2N CSEPN WEN OEN
TESTN XIN XOUT DFMS AS BAUDCLK P1 [7] P1 [6] SCL/P1 [4] VSS VDD P1 [5] SDA/P1 [3] P1 [2] P1 [1] P1 [0] VSS D7 D6 D5 D4 D3 D2 D1 D0
FP100
Fig.1 Pin connections - top view. Pin 1 is identified by moulded spot and by coding orientation. See Table 1 for detailed pin descriptions.
CLOCK & BAUD GENERATOR MEMORY INTERFACE WATCHDOG & POWER CONTROL INTERRUPT CONTROL
I/O PORTS
KEYPAD INTERFACE ACEBus INTERFACE
6303R MICROPROCESSOR UART (SCI) TIMER I/O PORTS
0·5K ROM 6K RAM
I2C BUS INTERFACE 23PULSE WIDTH MODULATOR
ORDERING INFORMATION
Industrial temperature range. TQFP 100-lead 14314mm, 0·5mm pitch package (FP100) ACE9050D / IG / FP8N: trays and dry packed ACE9050D / IG / FP8Q: tape mounted and dry packed
AMPS / TACS DATA MODEM IFC COUNTER SAT MANAGEMENT TONE GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply voltages VDD, VDDM Storage temperature Operating temperature Voltage on any pin 20·5V to 16V 255°C to 1150°C 240°C to 185°C VSS20·5V to VDD10·5V
Fig.2 ACE9050 simplified block diagram
ACE9050
SYNTHDATA SYNTHCLK DTFG LATCH0 LATCH1 LATCH3
72 73 82 80 78 75 SYNTHDATA SYNTHCLK DTFG LATCH0 ONRAD SINTSLEEP C1008 IRQSEND IRQREC PORT3[6] PORT4[7]
PULSE WIDTH MODULATOR
DAC1 DAC2
OUT2 [1] CONTROL 5 [0] } POPROTR5T[5:4] OUT2 [2] LATCH2
MUX #1
MUX CONTROL
98
ACE SERIAL INTERFACE
}INTERRUPTS
PWM #1 PWM #2
MRI IRW ID[7:0]
OUTP2 [1]/ PWM1 OUTP2 [2]/ PWM2/ LATCH2
LSICOM0 LSICOM1 LATCH1 LSICOM2 LSICOM3 LATCH3 LSICOM4 LSICOM5 LATCH2 LSICOM6 MRI IRW ID[7:0] STR_WIDTH
MUX #2
81
INTERNAL PORTS
EXTERNAL PORTS
OUT2 [7] 79 76 NOT BONDED TO MUX #2 TO MUX #1 TO CPUCL PIN POWERDET SERV 3 54, 53, 52
TO MUX #2 TO 6303 83 5 95 18-25 46-41 92,93 8 6 2 40,39,35-30 8 EMUL IP EMUL IP
REFER TO TEXT FOR INDIVIDUAL BIT FUNCTIONS
O/P IN EMULATION DATA INTERNAL ADDRESS
PORT3 [7:0] PORT4 [7:0] PORT5 [7:0]
PORT3 PORT4 PORT5
PORT3 PORT4 PORT5
O/P PORT2
OUT_PORT2
OUT2 [6] OUT2 [5:3] OUT2 [2] OUT2 [1] OUT2 [0]
OUTP2 [7] OUTP2 [6]
EMUL AS R/W D [7:0] A [7:0] A [13:8] A [15:14] BA [17:14] CSE2N CSEPN
BUS INTERFACE
EMUL ONLY EMUL IP EMUL DATA/AD IRW ID7:0 AD15:0
MRI IRW ID[7:0] LVN1
I/P PORT1
IN_PORT1 ID [7:0]
INP1 [7] INP1 [6] INP1 [4:2] INP1 [1:0]
INP1 [4:2]
RAM 6016 BYTES (IRAM)
AD [12:0] IRW IRAM
IRQE
EXT. INTERRUPTS
IRQPRT4-RESET IRQPRT5-MASK IRQPRT6-READ 5 4 59-55 66-69 2 70, 71
INRQ [1:0]
50-47 29 28
4
MEMORY BANK SWITCHING EPROM
BANK_SEL MRI IRW ID[4:0] AD[15:14]
ROM 512 BYTES (IROM) BOOT BLOCK
ID [7:0] AD [8:0] IRW IROM
KEYPORT/CHIP ID
KEYP R/W TO PORT KPOT O/P TRISTATE MRI IRW ID[7:0] ISDA ISCL
KPO [4:0] KPI [3:0]
IN_PORT1 OUT_PORT2 26
OEN
IRQPRT4
DECODER WEN
27
IRQPRT5 IRAM EPROM IROM IROME
ACE9050 REGISTER SELECTS MEMORY SELECTS
PORT4 [1] PORT3 [1]
6303 MICROPROCESSOR AND IRW READ/WRITE KERNEL
AD15:O ID7:0 EMUL ICN COUNTER I/P RESET MRI CLOCK E
PORT1 [7:0] PORT2 [4] PORT2 [3] BAUDCLK
8
7-9, 12-16 4 97 84 6
INTERRUPT IRQN 83BAUD
P1 [7:0] DFMS/P2 [4] DTMS/P2 [3] IRQN BAUDCLK
BAUD RATE CLOCK
PORT5 [2] ENABLE RESET I2C I2C_ADDR I2C_DATA I2C_CNTR ISCL P1 [4] P1 [3] I2C_INTERRUPT IRQTX IRQWS IRQBISAT IRQRX IRQREQ IRQSEND 8·064MHz IRQTO BRG MRI IRW ID[7:0]
IRQN I2C INTERRUPT IRQE (EXTERNAL INT.) IRQPRT0-RESET IRQPRT1-MASK IRQPRT2-READ
MRI IRW AD[15:0] SLEEP
BEEP ALARM RING GENERATOR (BAR) BAR
96 BAR BARENABLE BARHIGH BARLOW MRI ID[7:0] CLKBUS 126kHz
I2C_STAT I2C_CCR
I2C
ISDA INT
TESTN CLKBUS IRW ID[7:0]
INTERRUPT CONTROL INTERRUPT SOURCE MRI IRW ID[7:0]
OUT2 [0] 94 90 99 2 3 1 TO WATCHDOG AND I2C 63 62 51 89
TO 6303
ICN (EMUL) AFC/RXDATA
77 60
ICN
IFC COUNTER
IFFREQ (2432/256) STIFCN (START/RESET) PORT3 [0] PORT3 [5]
INTERRUPTS
PORT4 [4] PORT3 [3] PORT3 [7]
IRQRX IRQBISAT IRQWS IRQTX AFC/RXDATA NOMPLL MDMSLP ENMOD
MODEM
MODPRT0 MODPRT1 MODPRT2 ID [7:0] BARPORT TEST ACCESS ONLY TXDATA IRW MRI C1008 PORT5 [6] PORT4 [3] PORT3 [2] PORT5 P[1]
CLOCK GENERATOR
XOSC-PD TURBO ENSIS CLKENAB E (CPU CLOCK) CLKBUS C1008 LVN1 CPUCL
54kHz/450kHz
VDD VDDM VSS
11, 64, 65, 68 38 10, 17, 36, 37, 86, 87 INP1 [6] 74 91
CPUCL/ OUTP2 [0] C1008 ECLK XIN XOUT TESTN
WATCHDOG AND ATO
REWD MASTER RESET WATCHDOG AND RESET LOGIC RESATO FILTER ATO LOGIC IRQTO MRI LVN1
SAT MANAGEMENT
PORT4 [2] SELECT SAT GENERATOR SAT MUX
SERV MRN
TXDATA TXSAT RXSAT EXRESN
RXCD TXPOW
100 61
85
POFFN
CLKBUS IRW TESTN INP1 [7] POWDET PORT3 [4] UPOFFN
Fig. 3 detailed block diagram of ACE9050
2
ACE9050
FUNCTIONAL OVERVIEW
MICROPROCESSOR UNIT The processor unit is program compatible with the standard 6303R. It contains the following hardware: 8-bit CPU Serial Communication Interface: SCI (UART) 16-bit timer/counter 8-bit l/O port (P1) 2-bit l/O port (P2) The processor bus speed can be either 1·008 MHz or 2·016 MHz. An Emulation mode is provided whereby the internal 6303 is bypassed to allow software development on a standard 6303 In-Circuit Emulator (ICE). MEMORY The ACE9050 contains 512 bytes ofROM and 6144 bytes of RAM internally. The ROM code facilitates system initiation after a reset and the programming of FLASH memory via the 6303 SCI (UART). The Internal RAM area represents the total RAM requirement anticipated for a cellular phone. BUS INTERFACE and MEMORY BANK SWITCHING These blocks create the Data, Address and Control lines for the external memory. The external address bus is expanded from the standard 16 bits up to 18 bits by a banked addressing scheme. This increases the memory address space from 64K to 256K. Two programmable Chip Selects (CSEPN and CSE2N) are generated. The Memory Interface will operate down to 13V, allowing the use of low voltage memory parts. In Emulation mode the external processor controls the ACE9050 via the Bus Interface block. EXTERNAL PORTS The ACE9050 contains two Keypad Interface ports, two maskable external interrupts, and both Input and Output ports. These are in addition to the 6303 bidirectional Port1 and Port2. The Output port provides two high current outputs for driving LEDs. DECODER and INTERRUPT CONTROL The Decoder block memory maps ACE9050 register locations onto the processor's address space. The Interrupt Control block handles both internal and external interrupt sources. These are fed into control logic allowing individual masking and reset by software. The Interrupt control logic output is internally connected to the 6303 IRQ and also drives an external pin. ACE SERIAL INTERFACE (SINT) and I2C Three serial interface protocols are supported: UART, I2C and ACEBus. The 6303 provides a UART interface via the SCI block. The ACE9050 I2C block provides an I2C interface with both Master and Slave capability. The ACEBus is designed for use with the ACE Chipset and has a data rate of just over 1MBits/sec. Three Latch pulse are available to target data at the relevant IC and control the ACE9030 Synthesiser. BEEP, ALARM and RING TONE GENERATOR (BAR) The BAR Generator is intended to drive an acoustic tone transducer. It has a programmable single digital pulse train output. MODEM and SAT MANAGEMENT The Modem provides two way data transfer and SAT management over the radio link between a base station and phone handset. AMPS and TACS data rates are supported . The Modem block contains: Digital Discriminator, Data Decoder and Word Synchronising hardware. Various modes can be selected by software. A squelch level is also set by software so that the quality of each data byte can be assessed. SAT detection and generation at the standard three frequencies 5970Hz, 6000Hz and 6030Hz is included. WATCHDOG and POWER CONTROL (ATO) The Watchdog function will provide an internal and external Reset if the processor does not make a write access to a defined address every 4 seconds. An Autonomous Time Out circuit (ATO) will drive the POFFN output low if Transmitter power is detected without Receiver power, independent of any processor operation. POFFN must be used in conjunction with external regulators to control power to the mobile handset. IF CONTROL COUNTER (IFC) The Intermediate Frequency Control (IFC) Counter is used as part of an AFC Loop. The IFC Counter provides a pulse after a set number of IF input pulses. The IFC Counter output is connected to the 6303 timer input and an external pin (ICN). TWIN PULSE WIDTH MODULATORS Two independently programmable Pulse Width Modulators (PWMs) are available. These provide digital output pulse trains, controllable by software. The output can be filtered externally to provide a DAC function. Typical applications are battery charging control and LCD contrast control. CLOCK GENERATOR The Clock Generator provides all the various internal and external clocks from a single 8·064 MHz source. The source can either be an external crystal or the ACE9030.
3
ACE9050
PIN DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Name TESTN XIN XOUT DFMS/P2 [4] AS BAUDCLK P1[7] P1[6] P1[4]/SCL VSS VDD P1[5] P1[3]/ SDA P1[2] P1[1] P1[0] VSS D7 D6 D5 D4 D3 D2 D1 D0 OEN WEN CSEPN CSE2N A0 A1 A2 A3 A4 A5 VSS VSS VDDM A6 A7 A8 A9 A10 A11 A12 A13 BA14 BA15 BA16 BA17 RXSAT INP1 [2] INP1 [3] INP1 [4] KPO [0] KPO [1] KPO [2] KPO [3] KPO [4] AFC/RXDATA TXPOW TXSAT TXDATA VDD VDD Type I I O I/O I O (I) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O Block CLK/WDATO CLK CLK CPU BINT BAUD CPU CPU CPU / I2C CPU CPU / I2C CPU CPU CPU BINT BINT BINT BINT BINT BINT BINT BINT DEC DEC MEMB MEMB BINT BINT BINT BINT BINT BINT Description Connect to VDD Crystal connection CMOS input: 8·064 MHz Crystal connection CPU Port2 bit 4 or Serial interface (SCI) output Address strobe (Latch Address during Emulation) Baud Rate Gen. output for Emulation (lnput in test mode) PORT 1 of CPU PORT 1 of CPU PORT 1 of CPU/I2C SCL Ground Digital Supply PORT 1 of CPU PORT 1 of CPU/I2C SDA PORT 1 of CPU PORT 1 of CPU PORT 1 of CPU Ground Data bus (and Emulation Address A7 Input) Data bus (and Emulation Address A6 Input) Data bus (and Emulation Address A5 Input) Data bus (and Emulation Address A4 Input) Data bus (and Emulation Address A3 Input) Data bus (and Emulation Address A2 Input) Data bus (and Emulation Address A1 Input) Data bus (and Emulation Address A0 Input) Output Enable Write Enable C/S External EPROM C/S External EEPROM Address bus Address bus Address bus Address bus Address bus Address bus Ground Ground Digital Supply for Memory Interface (pins18-35, 38-50) Address bus Address bus Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Input during Emulation) Address bus (Extended Address: From Bank Select Register) Address bus (Extended Address: From Bank Select Register) Address bus (Extended Address: From Bank Select Register) Address bus (Extended Address: From Bank Select Register) Received SAT input Bit 2 Input Port1 Bit 3 Input Port1 Bit 4 Input Port1 Keypad scan output/output port Keypad scan output/output port Keypad scan output/output pon Keypad scan output/output port Keypad scan output/output port 54/450kHz IF input fromACE9030 Power detect from transmitter SAT Output TACS / AMPS Modem Output Digital Supply Digital Supply Internal PU None None PU PU None None None None None None None None None None None None None None None None None None None None None None None None None None None None Cont...
O O O (I) O (I) O (I) O (I) O (I) O (I) O O O O I I I I O O O O O I I O O
BINT BINT BINT BINT BINT BINT BINT BINT MEMB MEMB MEMB MEMB MODEM EPORT EPORT EPORT EPORT EPORT EPORT EPORT EPORT IFC/MODEM WDATO MODEM MODEM
Table 1
4
ACE9050
Pin 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name KPI [3] KPI [2] KPI [1] KPI [0] INRQ1 INRQ0 SYNTHDATA SYNTHCLK SERV LATCH3 OUTP2 [6] ICN LATCH1 OUTP2[7] LATCH0 OUTP2[2]/PWM2/ LATCH2 DTFG EMUL IRQN POFFN VSS VSS VDD EXRESN C1008 MRN A15 A14 CPUCL/OUTP2 [0] R/W BAR DTMS OUTP2 [1]/PWM 1 ECLK RXCD Type I I I I I I O O I O O O (I) O O O O I/O I O (I) O Block EPORT EPORT EPORT EPORT EPORT EPORT SINT SINT WDATO SINT EPORT IFC SINT EPORT SINT PWM SINT BINT/CPU CPU WDATO Description Keypad scan input/input port Keypad scan input/input port Keypad scan input/input port Keypad scan input/input port External Interrupt (also Bit1 Input Port1) External Interrupt (also Bit0 Input Port1) SynthBus Data Line SynthBus 126kHz Clock 1 = Service Mode Latch, programmable length. (To ACE9030, LATCHC pin) Output Port2 Bit 6: High Current Driver IF Counter Output for Emulation (input in Test mode) Latch O/P (To ACE9030 receiver Interface, LATCHB pin) Output Port2 Bit 7: High Current Driver Latch O/P (To ACE9040, LEN ) Output Port2 Bit 2/Pulse Width Modulator #2 Output/ SynthBus Latch O/P. Bidirectional serial inter-chip data, to/from the ACE9030 1 = CPU Emulation Mode CPU Interrupt for Emulation (input in Test mode) Power On/Off Ground Ground Digital Supply External reset output 1·008MHz Clock for ACEBus, ACE9030 and ACE9040 0 = Chip reset Address input for Emulation only Address input for Emulation only 8.064MHz clock/Out Port 2 bit 0 Read/Write (Input during Emulation) Beep, Alarm, Ring Tone Output CPU Port 2 bit 3 or Serial interface (SCI) input Output Port 2 Bit 1/Pulse Width Modulator #1 Output Processor Clock (Input during Emulation) Carrier detect from RX Internal PD PD PD PD PD PD None PU None PD None PU PU None None None None
O O I I I O O (I) O I/O O O (I) I
WDATO CLK WDATO BINT BINT CLK/EPORT BINT BAR CPU PWM CLK WDATO
Table 1 (continued)
ABBREVIATIONS BAR Beep, Alarm and Ring tone generator BAUD Baud Rate generator BINT Bus Interface MEMB Memory Bank switching CLK Clock generator CPU 6303 microprocessor unit DEC Decoder EPORT External Port I2C IFC MODEM PWM SINT WDATO PU PD I2C interface IF Control counter AMPS/TACS Modem Pulse Width Modulator and MUX Serial Inter-chip interface Watchdog/Autonomous Time Out Internal Pullup resistor present Internal Pulldown resistor present
UNUSED INPUTS Input or bidirectional pins must have a suitable pullup or pulldown reststor if they are configured as inputs, with no external drive. Some inputs have an internal pullup or pulldown resistor of the order of 100k; this value is suitable if the pin is not subject to excessive noise or residual current greater than 15µA. If the pins shown in Table 2 are not used in the system, an external resistor will be required. Pin 4 7 8 9 12 13 14 DFMS P1 [7] P1 [6] P1 [5] P1 [4] P1 [3] P1 [2] Name Pin 15 16 51 52 53 54 60 Name P1 [1] P1 [0] RXSAT INP1 [2] INP1 [3] INP1 [4] AFC_IN/RXDATA Pin 61 74 82 91 97 100 Name TXPOW SERV DTFG (Requires programming resistor) MRN DTMS RXCD
NOTE: P1 [7:0], DFMS and DTMS are configured as inputs upon reset.
Table 2
5
Others parts begin by ac
AC-1 AC-2 AC-3 AC-4 AC-5 AC-6 AC-7 AC-8 AC-9 AC-10 AC-11 AC-12 AC-13 AC-14 AC-15
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