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Details, datasheet, quote on part number:MT8809AC
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| Part: | MT8809AC |
| Category: | Communication => DSL (Digital Subscriber Line) => DSL Analog Front Ends |
| Description: | ISO-cmos 8 X 8 Analog Switch Array |
| Company: | Mitel Networks Corporation |
| Datasheet: | Download MT8809AC datasheet File size : 57 kB |
| Request For quote: | Find where to buy MT8809AC
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Datasheet text preview:
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ISO-CMOS MT8809 8 x 8 Analog Switch Array
Feature s
· · · · · · · · · · I nt er n al control latches and address decoder S ho r t setup and hold times W i de operating voltage: 4.5V to 13.2V 12 V pp analog signal capability R O N 65 max. @ V DD= 12 V, 25°C R O N 10 @ V D D=1 2V, 25°C Fu ll CMOS switch for low distortion M in im um feedthrough and crosstalk Lo w power consumption ISO-CMOS technology I nt er n al pull-up resistor for RESET pin
I SSUE 2
November 1988
O rd er i ng Information M T 8 80 9 A C 28 Pin Ceramic DIP M T 8 80 9 A E 28 Pin Plastic DIP M T 8 80 9 A P 28 Pin PLCC -40° to 85°C
Des cr ip t io n
The Mitel MT8809 is fabricated in MITEL's ISOCM OS technology providing low power dissipation and high reliability. The device contains a 8 x 8 array of crosspoint switches along with a 6 to 64 line dec oder and latch circuits. Any one of the 64 switches can be addressed by selecting the appropriate six address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. Chip Select (CS) allows the cros spoint array to be cascaded for matrix e x p a n s io n .
Ap p l ic a t io n s
· · · · · · K ey systems P B X systems M obi le radio Tes t equipment /instrumentation A na log / di git a l multiplexers A ud io/ Vi de o switching
CS
STROBE
DATA RESE T
VDD
VSS
1 AX0
1 ················
AX1 AX2 AY0 AY1 AY2 64 64
8x8 6 to 64 Deco der Latch e s Switch Array
Xi I/O (i= 0-7 )
···················
Yi I/O (i=0-7)
F i g ur e 1 - Functional Block Diagram
3- 21 3-21
MT8809
ISO-CMOS
AY2 ST ROBE CS DATA VSS X0 X2 X4 X6 RES ET Y7 Y6 Y5 Y4
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
AY1 AY0 AX2 AX1 AX0 X1 X3 X5 X7 VDD Y0 Y1 Y2 Y3
4 3 2 1 28 27 26
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DATA CS STROBE AY2 AY 1 AY0 AX2
28 PIN CERDIP/PLASTIC DIP
Fi g u re 2 - Pin Connections
Pin Description
Pin # 1 2 Name AY2 AY2 Address Line (Input). Description
STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes low and DATA must be stable on the rising edge of STROBE. Active Low. CS DATA VSS X0, X2, X4, X6 RE S E T Chip Select (Input): this is used to select the device. Active Low. DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. Ground Reference. X0, X2, X4 and X6 Analog (Inputs/Outputs): these are connected to the X0, X2, X4 and X6 rows of the switch array. Master RESET (Input): this is used to turn off all switches regardless of the condition of CS. A 100k internal pull-up resistor is also provided. This can be used in conjunction with a 0.1µF capacitor (connected to the RESET pin) to perform power-on reset of the device. Active Low. Y7 - Y0 Analog (Inputs/Outputs): these are connected to the Y0 - Y7 columns of the switch array. Positive Power Supply. X7, X5, X3 and X1 Analog (Inputs/Outputs): these are connected to the X7, X5, X3 and X1 rows of the switch array.
3 4 5 6-9 10
11-18 19 20-23 24-26 27, 28
Y7 - Y0 V DD X7, X5, X3, X1
AX0-AX2 AX0 - AX2 Address Lines (Inputs). AY0, AY1 AY0 and AY1 Address Lines (Inputs).
3-2 2
Y6 Y5 Y4 Y3 Y2 Y1 Y0
12 13 14 15 16 17 18
VSS X0 X2 X4 X6 RESET Y7
5 6 7 8 9 10 11
25 24 23 22 21 20 19
AX1 AX0 X1 X3 X5 X7 VDD
28 PIN PLCC
ISO-CMOS
Functi onal Description
The MT8809 is an analog switch matrix with an array size of 8 x 8. The switch array is arranged such that there are 8 columns by 8 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high degree of isolation when turned off. The control memory consists of a 64 bit write only RAM in which the bits are selected by the address inputs (AY0-AY2, AX0-AX2). Data is presented to the memory on the DATA input. Data is async hronously written into memory whenever both the CS (Chip Select) and STROBE inputs are low and are latched on the rising edge of STROBE. A logical "1" written into a memory cell turns the corresponding crosspoint switch on and a logical "0" turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are alt ered when data is written into memory. The remaining switches retain their previous states. Any combinat ion of X and Y inputs/outputs can be int erconnected by establishing appropriate patterns in the control memory. A logical "0" on the RESET input will asynchronously return all memory locations to logical "0" turning off all crosspoint switches regardless of whether CS is high or low.
MT8809
Addres s Decode
The six address inputs along with the STROBE and CS (Chip Select) are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be high and CS must go low while the address and data are set up. Then the STROBE input is set low and then high causing the data to be latched. The data can be changed while STROBE is low, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on the rising edge of STROBE in order for correct data to be written to the latch.
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