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Details, datasheet, quote on part number:MT8812AC
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| Part: | MT8812AC |
| Category: | Communication => DSL (Digital Subscriber Line) => DSL Analog Front Ends |
| Description: | ISO-cmos 8 X 12 Analog Switch Array |
| Company: | Mitel Networks Corporation |
| Datasheet: | Download MT8812AC datasheet File size : 54 kB |
| Request For quote: | Find where to buy MT8812AC
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Datasheet text preview:
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ISO-CMOS MT8812 8 x 12 Analog Switch Array
Feature s
· · · · · · · · · I nt er n al control latches and address decoder S ho r t set-up and hold times W i de operating voltage: 4.5V to 14.5V 14 V pp analog signal capability R O N 65 max. @ V DD= 14 V, 25°C R O N 10 @ V DD= 14 V, 25°C Fu ll CMOS switch for low distortion M in im um feedthrough and crosstalk Lo w power consumption ISO-CMOS technology
I SSUE 5
November 1988
O rd er i ng Information M T 8 81 2 A C 40 Pin Ceramic DIP M T 8 81 2 A E 40 Pin Plastic DIP M T 8 81 2 A P 44 Pin PLCC 0° to 70°C
Des cr ip t io n
The Mitel MT8812 is fabricated in MITEL's ISOCM OS technology providing low power dissipation and high reliability. The device contains a 8 x12 array of crosspoint switches along with a 7 to 96 line dec oder and latch circuits. Any one of the 96 switches can be addressed by selecting the appropriate seven input bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input.
Ap p l ic a t io n s
· · · · · P B X systems M obi le radio Tes t equipment /instrumentation A na log / di git a l multiplexers A ud io/ Vi de o switching
STROBE
DATA RESET
VDD
VSS
1 AX 0 AX 1 AX2 A X3 AY 0 AY 1 AY 2 96
1 ················
8 x 12 7 to 96 Decod er L atche s Switch Array
96
Xi I/O ( i=0-1 1)
···················
Yi I/O (i=0-7)
F i g ur e 1 - Functional Block Diagram
3-27
MT8812
ISO-CMOS
40 PIN CERDIP/PLASTIC DIP
Fi g u re 2 - Pin Connections
Pin Description
Pin #* 1 2 3 4,5 6,7 8-13 Nam e Y3 AY2 RESET AX3,AX0 NC X6-X11 Description Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array. Y2 Address Line (Input). Master RESET (Input): this is used to turn off all switches. Active High. X3 and X0 Address Lines (Inputs). No Connection. X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch array. 14 NC No Connection. 15 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array. 16 NC No Connection. 17 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array. 18 STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. 19 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array. Ground Reference. 20 VSS 21 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array. 22, 23 AX1,AX2 X1 and X2 Address Lines (Inputs). 24, 25 AY0,AY1 Y0 and Y1 Address Lines (Inputs). 26, 27 NC No Connection. 28 - 33 X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch array. 34 NC No Connection. 35 Y0 Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array. 36 NC No Connection. 37 Y1 Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array. 38 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. 39 Y2 Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array. Positive Power Supply. 40 VDD
* Plastic DIP and CERDIP only. 3-2 8
Y7 Y6 STRO B E Y5 VS S Y4 AX1 AX2 AY0 AY1 NC 44 PIN PLCC
Y3 AY2 RESE T AX3 AX0 NC NC X6 X7 X8 X9 X10 X11 NC Y7 NC Y6 ST ROBE Y5 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD Y2 DATA Y1 NC Y0 NC X0 X1 X2 X3 X4 X5 NC NC AY1 AY0 AX2 AX1 Y4
NC NC X6 X7 X8 X9 X10 X11 NC NC NC
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28
AX 3 R E S ET AY 2 Y3 VDD Y2 DAT A Y1 Y0 NC NC X0 X1 X2 X3 X4 X5 NC NC NC
NC AX 0
ISO-CMOS
Functi onal Description
The MT8812 is an analog switch matrix with an array size of 8 x 12. The switch array is arranged such that there are 8 columns by 12 rows. The columns are referred to as the Y input/output lines and the rows are the X input/output lines. The crosspoint analog switch array will interconnect any X line with any Y line when turned on and provide a high degree of isolat ion when turned off. The control memory consist s of a 96 bit write only RAM in which the bits are selected by the address input lines (AY0-AY2, AX 0-AX 3). Data is presented to the memory on the DATA input line. Data is asynchro-nously written into memory whenever the STROBE input is high and is lat ched on the falling edge of STROBE. A logical "1" written into a memory cell turns the corresponding crosspoint switch on and a logical "0" turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are alt ered when data is written into memory. The remaining switches retain their previous states. Any combinat ion of X and Y lines can be interconnected by establishing appropriate patterns in the control memory. A logical "1" on the RESET input line will async hronously return all memory locations to logical "0" turning off all crosspoint switches.
MT8812
Addres s Decode
The seven address lines along with the STROBE input are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latc hes. To write to a location, RESET must be low while the address and data lines are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STR OBE is high, however, the corresponding switch will turn on and off in accordance with the data. Data must be stable on the falling edge of STROBE in order for correct data to be written to the latch.
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