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Details, datasheet, quote on part number:MT8814
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| Part: | MT8814 |
| Category: | Communication => DSL (Digital Subscriber Line) => DSL Analog Front Ends |
| Description: | ISO-cmos 8 X 12 Analog Switch Array |
| Company: | Mitel Networks Corporation |
| Datasheet: | Download MT8814 datasheet File size : 60 kB |
| Request For quote: | Find where to buy MT8814
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Datasheet text preview:
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ISO-CMOS MT8814 8 x 12 Analog Switch Array
Feature s
· · · · · · · · · · I nt er n al control latches and address decoder S ho r t set-up and hold times W i de operating voltage: 4.5V to 13.2V 12 V pp analog signal capability R O N 65 max. @ V DD= 12 V, 25°C R O N 10 @ V D D=1 2V, 25°C Fu ll CMOS switch for low distortion M in im um feedthrough and crosstalk S ep ar at e analog and digital reference supplies Lo w power consumption ISO-CMOS technology
I SSUE 2
November 1988
O rd er i ng Information M T 8 81 4 A C 40 Pin Ceramic DIP M T 8 81 4 A E 40 Pin Plastic DIP M T 8 81 4 A P 44 Pin PLCC -40° to 85°C
Des cr ip t io n
The Mitel MT8814 is fabricated in MITEL's ISOCM OS technology providing low power dissipation and high reliability. The device contains a 8 x 12 array of crosspoint switches along with a 7 to 96 line dec oder and latch circuits. Any one of the 96 switches can be addressed by selecting the appropriate seven address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. VSS is the ground reference of the digital inputs. The range of the analog signal is from VDD to VEE. Chip Select (CS) allows the cros spoint array to be cascaded for matrix e x p a n s io n .
Ap p l ic a t io n s
· · · · · · K ey systems P B X systems M obi le radio Tes t equipment /instrumentation A na log / di git a l multiplexers A ud io/ Vi de o switching
CS
STROBE
DAT A RESET
V DD
V EE
VS S
AX0 AX1 AX2 AX3 AY0 AY1 AY2
1
1 ················
8 x 12 7 to 96 Deco de r Latch e s Switch Arra y
96 96
Xi I/O (i= 0- 11 )
···················
Yi I/O (i=0-7)
F i g ur e 1 - Functional Block Diagram
3- 33 3-33
MT8814
ISO-CMOS
AX3 RESET AY2 Y3 VDD Y2 DATA Y1 CS Y0 NC X0 X1 X2 X3 X4 X5 NC NC NC 44 PIN PLCC
40 PIN CERDIP/PLASTIC DIP
Fi g u re 2 - Pin Connections
Pin Description
Pin #* 1 2 3 4,5 6,7 8-13 14 15 16 17 18 Name Y3 AY2 RESET AX3,AX0 NC X6-X11 NC Y7 VSS Y6 S T ROB E Description Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array. Y2 Address Line (Input). Master RESET (Input): this is used to turn off all switches regardless of the condition of CS. Active High. X3 and X0 Address Lines (Inputs). No Connection. X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch array. No Connection Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array. Digital Ground Reference . Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array. STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array. Negative Power Supply. Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array. X1 and X2 Address Lines (Inputs). Y0 and Y1 Address Lines (Inputs). No Connection. X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch array. No Connection. Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array. Chip Select (Input): this is used to select the device. Active High. Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array. DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array. Positive Power Supply.
19 20 21 22, 23 24, 25 26, 27 28 - 33 34 35 36 37 38 39 40
Y5 VEE Y4 AX1,AX2 AY0,AY1 NC X 5-X 0 NC Y0 CS Y1 DATA Y2 V DD
* Plastic DIP and CERDIP only
3-3 4
NC Y6 STRO BE Y5 VEE Y4 AX1 AX2 AY0 AY1 NC
Y3 A Y2 RE SET A X3 AX0 NC NC X6 X7 X8 X9 X1 0 X1 1 NC Y7 VSS Y6 S TROBE Y5 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD Y2 DATA Y1 CS Y0 NC X0 X1 X2 X3 X4 X5 NC NC AY1 AY0 AX2 AX1 Y4
AX0 NC X6 X7 X8 X9 X10 X11 NC Y7 VSS
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28
NC NC
ISO-CMOS
Functi onal Description
The MT8814 is an analog switch matrix with an array size of 8 x 12. The switch array is arranged such that there are 8 columns by 12 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in which the bits are selected by the address inputs (AY0-AY2, AX0-AX3). Data is presented to the memory on the DATA input. Data is async hronously written into memory whenever both the CS (Chip Select) and STROBE inputs are high and are latched on the falling edge of STROBE. A logical "1" written into a memory cell turns the corresponding crosspoint switch on and a logical "0" turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are alt ered when data is written into memory. The remaining switches retain their previous states. Any combinat ion of X and Y inputs/outputs can be int erconnected by establishing appropriate patterns in the control memory. A logical "1" on the RESET input will asynchronously return all memory locations to logical "0" turning off all crosspoint switches regardless of whether CS is high or low. Two voltage reference pins (VSS and VEE) are provided for the MT8814 to enable switching of negative analog signals . The range for digital signals is from VDD to VSS while the range for analog signals is from V DD to VEE. V SS and V EE pins can be tied together if a single voltage reference is needed.
MT8814
Addres s Decode
The seven address inputs along with the STROBE and CS (Chip Select) are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low and CS must go high while the address and data are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on the falling edge of STROBE in order for correct data to be written to the latch.
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