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Details, datasheet, quote on part number:MT88L85
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| Part: | MT88L85 |
| Category: | Communication => Telephony => Line Interface |
| Description: | 3v Integrated Dtmftransceiver With Power Down & Adaptive Micro Interface |
| Company: | Mitel Networks Corporation |
| Datasheet: | Download MT88L85 datasheet File size : 359 kB |
| Request For quote: | Find where to buy MT88L85
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Datasheet text preview:
MT88L85
®
3V Integrated DTMF Transceiver with Power Down & Adaptive Micro Interface Advance Information
Feature s
· · · · · · · · · E x t er n al power down pin Lo w voltage operation (2.7V - 3.6V) C en t r al office quality DTMF transmitter/ r e c e iv e r Lo w power consumption H i gh speed adaptive micro interface A dj us t ab le guard time A ut om a t ic tone burst mode C al l progress tone detection to -30dBm D T M F transmitter/receiver power down via register control
I SSUE 1
May 1995
O rd er i ng Information M T 8 8L 8 5 A E MT 8 8 L 8 5 A N M T 8 8L 8 5 A P -40°C to 24 Pin Plastic DIP 24 Pin SSOP 28 Pin PLCC +85°C
Ap p l ic a t io n s
· · · · · C r e dit card systems P ag ing systems R ep ea te r systems/mobile radio I nt er c o nn e c t dialers P er s o na l computers
The receiver section is based upon the industry standard MT8870 DTMF receiver while the transm it ter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones. The MT88L85 utilizes an adaptive micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic. The MT88L85 provides enhanced power down feat ures. The transmitter and receiver may independent ly be powered down via register control. A full chip power down pin provides simple pow er and control capability.
De s c r i p t i o n
The MT88L85 is a monolithic DTMF transceiver with call progress filter. It is fabricated in CMOS technology offering low power consumption and high reliability.
TON E
D/A Converte rs
Row and Colum n Counters
Transmit Data Register Status Register
Data Bus Buffer
D0 D1 D2 D3
Tone Burst Gating Cct. IN+ I NGS OSC1 OSC2 Oscillator Circuit Bi as Circuit + Dia l Tone Fil ter
Con tro l Logic
Interr upt Logic IRQ/CP
High Group Filter Low Group Filter Control Logic
Digital Algorithm and Code Convert er
Control Register A Control Register B I/O Control
DS/RD CS R/W/WR RS0
St eering Logic
Receive Data R egister
VDD VRef
VSS
PWDN
ESt
St/GT
F i g ur e 1 - Functional Block Diagram
4-71
MT88L85
IN+ INGS VRef VSS OSC1 OSC2 NC NC TONE R/W/WR CS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD St/GT ESt D3 D2 D1 D0 NC PWDN IRQ/CP DS/ R D RS0 GS NC ININ+ VDD St/GT ESt 5 6 7 8 9 10 11 4 3 2 1 28 27 26 ·
Advance Information
24 PIN DIP/SSOP
Fi g u re 2 - Pin Connections
Pin Description
Pin # 24 1 2 3 4 5 6 7 10 11 12 13 14 15 28 1 2 4 6 7 8 9 12 14 15 17 18 Name IN+ I NGS VRef VSS OSC1 OSC2 TONE CS RS 0 Non-inverting op-amp input. Inverting op-amp input. Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference Voltage output (VDD/2). Ground (0V). Oscillator input. This pin can also be driven directly by an external clock. Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally. Output from internal DTMF transmitter. Chip Select input. This signal must be qualified externally by either address strobe (AS), valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12. Register Select input. Refer to Table 3 for bit interpretation. CMOS compatible. Description
13 R/W(WR) (Motorola) Read/Write or (Intel) Write microprocessor input. CMOS compatible.
DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is only required when the device is being accessed. CMOS compatible. IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes low when a valid DTMF tone burst has been transmitted or received. In call progress mode, this pin will output a rectangular signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter, see Figure 8. PW DN Power Down (input). Active High. Powers down the device and inhibits the oscillator. IRQ and TONE output are high impedance. Data bus is held in tri-state. This pin is internally pulled down. Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1 (Intel). TTL compatible. Early Steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. Positive power supply (3V typ.).
16
19
14- 1817 21 18 22
D 0 - D3 ESt
19
23
St/GT
20
4-7 2
24
VDD
TONE R/W/WR CS RS0 NC DS/RD IRQ/CP
12 13 14 15 16 17 18
NC VRef VSS OSC1 OSC2 NC NC
25 24 23 22 21 20 19
NC D3 D2 D1 D0 NC PW DN
28 PIN PLCC
Advance Information
Pin Description
Pin # 24 28
16, 20, 25
MT88L85
Name NC No Connection.
Description
8,9 3,5, 17 10,11
Functi onal Description
The MT88L85 Integrated DTMF Transceiver consists of a high performance DTMF receiver with an int ernal gain setting amplifier and a DTMF generator, which employs a burst counter to synthesize precise tone bursts and pauses. A call progress mode can be selected so that frequencies within the specified pas sband can be detected. The adaptive micro int erface allows microcontrollers, such as the 68H C 11 , 80C51 and TMS370C50, to access the MT88L85 internal registers.
Rec eiv er Section
Separation of the low and high group tones is achiev ed by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filt ers, the bandwidths of which correspond to the low and high group frequencies (see Table 1). The filters als o incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting. Lim it ing is performed by high-gain comparators which are provided with hysteresis to prevent detec tion of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals.
MT8 8L 85 IN+ IN-
P o wer Down
The MT88L85 provides enhanced power down functionality to facilitate minimization of supply current consumption. DTMF transmitter and receiver circuit blocks may be independently powered down via register control. When asserted, the RxEN control bit powers down all analog and digital circuitry associated solely with the DTMF and Call Pr ogress receiver. The TOUT control bit is used to dis able the transmitter and put all circuitry assoc iated only with the DTMF transmitter in power dow n mode. With the TOUT control bit asserted, the TONE output pin is held in a high impedance (floating) state. When both power down control bits are asserted, circuits utilized by both the DTMF transm itter and receiver are also powered down. This includes the crystal oscillators, and the VRef generator. In addition, the IRQ , TONE output and DATA pins are held in a high impedance state. Finally, the whole device is put in a power down state when the PWDN pin is asserted.
C
RIN
RF VOLTAGE GAIN (AV) = RF / RIN
GS VRef
Fi g u re 3 - Single-Ended Input Configuration
MT88 L8 5 C1 R1 IN+ INC2 R4 R5 GS
Input Configuration
R3 R2 VRef DIFFERENTIAL INPUT AMPLIFIER C1 = C2 = 10 nF R1 = R4 = R5 = 100 k R2 = 60k, R3 = 37.5 k R3 = (R2R5)/(R2 + R5) VOLTAGE GAIN INPUT IMPEDANCE (AV diff) - R5/R1 (Z diff ) = 2 R12 + (1/C)2
IN
The input arrangement of the MT88L85 provides a differential-input operational amplifier as well as a bias source (VRef), which is used to bias the inputs at VDD/ 2. Provision is made for connection of a feedback resistor to the op-amp output (GS) for gain adjust ment . In a single-ended configuration, the input pins are connected as shown in Figure 3. Figure 4 shows the necessary connections for a differential input configuration.
F ig u re 4 - Differential Input Configuration
4- 73
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