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Details, datasheet, quote on part number:MT8910-1
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| Part: | MT8910-1 |
| Category: | Communication => Telephony => Line Interface |
| Description: | CMOS St-bus Family Digital Subscriber Line Interface Circuit |
| Company: | Mitel Networks Corporation |
| Datasheet: | Download MT8910-1 datasheet File size : 429 kB |
| Request For quote: | Find where to buy MT8910-1
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Datasheet text preview:
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CMOS ST-BUSTM FAMILY MT8910-1 Digital Subscriber Line Interface Circuit Preliminary Information
Feature s
· · · · · · · · · · · · C om p at i ble with ISDN U-Interface standard Ov e r 40dB (@40 kHz) of loop attenuation Fu ll duplex transmission over single twisted pair A dv a nc e d echo cancelling technology H i gh performance 2B1Q line code Fu ll activation/deactivation state machine QS N R and line attenuation diagnostics Fr am e and superframe synchronization On - c hi p 15 second timer I ns er ti on loss measurement test signal & quiet mode M it e l ST-BUS compatible S in gl e 5V power supply
I SSUE 1
August 1993
O rd er i ng Information MT8910- 1A C 28 Pin Ceramic DIP MT8910- 1A P 44 Pin PLCC 0°C to +70°C
Description
The MT8910-1 Digital Subscriber Line Interface Cir cuit (DSLIC) is designed to provide ISDN basic rate access (2B+D) at the U-interface. Full duplex digital transmission at 160 kbit/s on a single twisted pair is achieved using echo cancelling hybrid (ECH) technology. This, in conjunction with the high performance 2B1Q line code, allows the DSLIC to meet the loop length requirements of the digital subscriber loops at the U-interface over the entire non-loaded telephone loop plant. The MT8910-1 is compatible with the complete range of Mitel Semiconductor ISDN components through the use of the ST-BUS interface.
Ap p l ic a t io n s
· · · · I S D N NT1 and NT2 DSL interface D i git a l PABX line cards and telephone sets D i git a l multiplexers and concentrators P ai r gain system
DST i CDST i
Transmit Interfa ce
Scrambler & Encoder
DAC and Tx Filter
+
Lo ut +
MRST F0b C4 b SF b F0o d MS0 MS1 NT/LT
C ontrol R eg ister
Jitter Compensator
Linear Echo Canceller
NonLinear Compensator
-
Lou t-
Tone Det ector
TRANS MIT/ R ECEIVE TIMING & CONTROL INTERFACE
Fram ing & Mai ntenance Decision Feedback Equalizer
2nd Order PDM ADC S tatus Reg iste r Quant izer F IR Digital Filter CDSTo DSTo Re ceive Interface De scra mbler, Decoder & Diagnostics Tim ing Adaptation Circuit Bias & Vol tage Ref.
Lin + Lin -
V SS
AVSS
VDD
AVDD
OSC2
OSC1
TSTin
TSTout TSTen VRef
VBi as
F i g ur e 1 - Functional Block Diagram
9-3
MT8910-1
Preliminary Information
TSTin AVS S NC Lout+ NC LoutLin+ LinVRe f VBias NC
28 PIN CERDIP
Fi g u re 2 - Pin Connections
Pin Description
Pin # Nam e DIP PLCC 1 2 3 4 1 3 5 6 LoutLout+ AVSS TSTin Line Out Minus. One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q signal, biased at VBias. Line Out Plus. One of a pair of differential analog outputs for the 80 kbaud/s 2B1Q signal, biased at VBias. Analog Ground. Tie to VSS. I/O Structure Test Input. When TSTen is high, TSTin is used as a source to all output drivers. Refer to "I/O Structure Test" in functional description for more details. Tie to V SS for normal operation. Description
5 6 7 8
8 12 13 14
CDSTi Control/Data ST-BUS Input. A 2048 kbit/s serial PCM/data input for the D- and C-channels in Dual mode. Unused in Single mode and should be connected to VSS. DSTi VSS DSTo Data ST-BUS Input. A 2048 kbit/s serial PCM/data input for the D-, C-, B1- and B2channels in Single mode. In Dual mode, only the B-channels are input. Ground. Data ST-BUS Output. A 2048 kbit/s serial PCM/data output for the D-, C-, B1- and B2channels in Single mode. In Dual mode, only the B-channels are output. This output is placed in high impedance during the unused channel times.
9
15
CDSTo Control/Data ST-BUS Output. A 2048 kbit/s serial PCM/data output for the D- and C- channels in Dual mode. It is placed in high impedance in Single mode, and during the unused channel times in Dual mode. F0od Delayed Frame Pulse Output. A 244 ns wide negative going pulse indicating the end of the active ST-BUS channel times of the device to allow for daisy-chaining of other ST-BUS devices. Active after channel 0 in Dual Port mode and Channel 3 in Single Port Mode.
10
16
11
18
TSTout I/O Structure Test Output. When TSTen is high, the TSTout provides the output of an XOR chain which is sourced from all digital inputs. Refer to "I/O Structure Test" in functional description for more details. Leave unconnected for normal operation. MS0 MS1 Mode Select 0. CMOS input. Refer to Table 1. Mode Select 1. CMOS input. Refer to Table 1.
12 13
9-4
19 20
TSTout M S0 M S1 NT/LT TSTen SFb NC C4b NC F0b NC 44 PIN PLCC
Lou tLo ut + AVSS TST in CDST i DST i V SS DST o CDST o F0o d TST ou t MS0 MS 1 NT/LT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Lin + Lin VRef VBias AVDD IC VD D MRST OSC1 OSC2 F0b C4 b SFb TSTe n
NC CDST i NC NC NC DSTi VSS DSTo CDSTo F0od NC
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28
NC AVDD NC NC NC IC VDD MRST OSC1 OSC2 NC
Preliminary Information
Pin Description (continued)
Pin # Nam e DIP PLCC 14 15 21 22 NT/LT TSTen Description
MT8910-1
NT/LT Mode Select. CMOS Input. When high, the DSLIC is setup in NT mode. When low, LT mode is selected. I/O Structure Test Enable Input. This active high input enables the built-in test of all digital input and output structures. Refer to "I/O Structure Test" in functional description for more details. Tie to VSS for normal operation. Superframe Pulse. In LT mode, an input pulse once every superframe (12 ms) which, when low during a falling edge of C4b within an F0b low pulse, sets the transmit superframe boundary. In NT mode, a 244 ns wide output pulse once every 12 ms indicating the boundary of the transmit superframe. In NT mode, the superframe timing is generated from the line signal time base and, as such, SFb will only be valid once the transceiver has achieved full activation.
16
23
SF b
17 18
25 27
C4 b F 0b
4096 kHz Data Clock. In LT mode, a 4096 kHz ST-BUS clock input. In NT mode, a 4096 kHz ST-BUS clock output frequency locked to the line signal. Frame Pulse. In LT mode, an 8 kHz input pulse indicating the start of the active ST-BUS channel times. In NT mode, an 8 kHz output pulse extracted from the line signal indicating the start of the active ST-BUS channel times. Oscillator Output. When the MT8910-1 operates with an External Clock (typically LT mode) connect OSC2 to the output of an external inverter providing a 10.24 MHz ±5ppm clock (see "10.24 MHz Clock Interface" section). When operating with a crystal (typically NT mode) connect one lead of the fundamental mode parallel resonator crystal (10.24 MHz ±50ppm in case of NT mode).
19
30
OSC2
20
31
OSC1
Oscillator Input. When the DSLIC operates with an External Clock (typically LT mode) connect OSC1 to the input of an external inverter (see Fig.11). When operating with a crystal (typically NT mode) connect the other lead of the fundamental mode parallel resonator crystal (10.24 MHz ±50ppm in case of NT mode).
21 22 23 24 25 26 27 28
32 33 34 38 41 42 43 44
2,4, 7, 9 -11, 17,2 4 26,2 8 29,3 5 36,3 7 39,4 0
MRS T VDD IC AVDD VBias VRef LinLin+ NC
Master Reset. Active low CMOS input performs a master reset of the DSLIC. Power Supply Input. Internal Connection. Leave unconnected. Analog Power Supply. Connect to VDD. Bias Voltage. Decouple to AVSS through a 1.0 µF ceramic capacitor. Reference Voltage. Decouple to AVSS through a 1.0 µF ceramic capacitor. Line Signal Input Minus. Internally biased at VBias. Line Signal Input Plus. Internally biased at VBias. No Connection. Leave circuit open.
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