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Details, datasheet, quote on part number:MT89L80
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| Part: | MT89L80 |
| Category: | Power Management => AC-DC Controllers/Converters => High & Low Side Switch |
| Description: | CMOS St-bus Family Digital Switch |
| Company: | Mitel Networks Corporation |
| Datasheet: | Download MT89L80 datasheet File size : 78 kB |
| Request For quote: | Find where to buy MT89L80
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Datasheet text preview:
CMOS ST-BUSTM FAMILY
MT89L80
Digital Switch Advance Information
Features
· · · · · · · · · · 3.3 volt supply 5V tolerant inputs and TTL compatible outputs. 256 x 256 channel non-blocking switch Accepts serial streams at 2.048Mb/s Per-chan n e l three-state control Patented per channel message mode Non-mul t i p l exe d microprocessor interface Mitel ST-BUS compatible Low power consumption: typical 15mW Pin compatible with the MT8980DP
DS5196
ISSUE 2
September 1999
O rd e r i n g Information MT89L80AP MT89L80AN 44 Pin PLCC 48 Pin SSOP
-40°C to +85°C
Description
This VLSI CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control, in a modern digital exchange, PBX or Central Office. It provides simultaneous connections for up to 256 64 kbit/s channels. Each of the eight ser ial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s ST-BUS stream. In addition, the MT89L80 provides microprocessor read and write access to individual ST-BUS channels.
Applications
· · · Key telephone systems PBX systems Small and medium voice switching systems
C4i
F0i RESET VDD VSS
**
ODE
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 Serial to Parallel Conver ter Data Memor y
Frame Counter
Output MUX Parallel to Serial Conver ter
STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7
Control Register Connection Memor y Control Interface
DS CS R/W A5/ A0 ** for 48-pin SSOP only
DTA D7/ D0
CSTo
Fi gur e 1 - Functional Block Diagram
2-3
MT89L80
NC STi2 STi1 STi0 DTA CSTo ODE STo0 STo1 STo2 NC
Advance Information
STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4
44 PIN PLCC
VSS DTA STi0 STi1 STi2 NC STi3 STi4 STi5 STi6 STi7 VDD RESET F0i C4i A0 A1 A2 NC A3 A4 A5 DS R/W
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
CSTo ODE STo0 STo1 STo2 NC STo3 STo4 STo5 STo6 STo7 VSS VDD D0 D1 D2 D3 D4 NC D5 D6 D7 CS VSS
NC A3 A4 A5 DS R/W CS D7 D6 D5 NC
18 19 20 21 22 23 24 25 26 27 28
6 5 4 3 2 1 44 43 42 41 40
48 PIN SSOP (JEDEC MO-118, 300mil Wide)
Fi gure 2 - Pin Connections
Pin Description
Pin # 44 48 PLCC SSOP 2 2 Name Description
DTA
Data Acknowledgment (5V Tolerant Three-state Output). This active low output indicates that a data bus transfer is complete. A pull-up resistor is required at this output.
3-5 7-11 12
3-5 7-11 12,36 13
STi0-2 ST-BUS Inputs 0 to 2 (5V-tolerant Inputs). Serial data input streams. These streams have data rates of 2.048Mbit/s with 32 channels. STi3-7 ST-BUS Inputs 3 to 7 (5V-tolerant Inputs). Serial data input streams. These streams may have data rates of 2.048Mbit/s with 32channels. VDD +3.3 Volt Power Supply.
RESET Device Reset ( 5v-tolerant input). This pin is only available for the 48-pin SSOP package.This active low input puts the device in its reset state. It clears the internal counters and registers. All ST-BUS outputs are set to the high impedance state. In normal operation. The RESET pin must be held low for a minimum of 100nsec to reset the device. F0i Frame Pulse (5V-tolerant Input). This is the input for the frame synchronization pulse for the 2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to reset on the next negative transition of C4i. 4.096 MHz Clock (5V-tolerant Input). ST-BUS bit cell boundaries lie on the alternate falling edges of this clock. Address 0-2 / Input Streams 8-10 (5V-tolerant Input). These are the inputs for the address lines on the microprocessor interface.
13
14
14 15-17
15 16-18
C4i A0-2
2-4
Advance Information
Pin Description (continued)
Pin # 44 48 PLCC SSOP 19-21 22 23 24 25-27 29-33 34 35-39 41-43 44 20-22 23 24 26 27-29 31-35 1, 25,37 38-42 44-46 47 Name Description
MT89L80
A3-5 DS R/W CS D7-D5 D4-D0 VSS
Address 3-5 / Input Streams 11-13 (5V-tolerant Input). These are the inputs for the address lines on the microprocessor interface. Data Strobe (5V-tolerant Input). This is the input for the active high data strobe on the microprocessor interface. Read/Write (5V-tolerant Input). This is the input for the read/write signal on the microprocessor interface - high for read, low for write. Chip Select (5V-tolerant Input). This is the input for the active low chip select on the microprocessor interface Data Bus (5V-tolerant I/O): These are the bidirectional data pins on the microprocessor interface. Data Bus (5V-tolerant I/O): These are the bidirectional data pins on the microprocessor interface. Ground.
STo7-3 ST-BUS Outputs 7 to 3 (5V-Tolerant Three-state Outputs). These are the pins for the eight 2048 kbit/s ST-BUS output streams. STo2-0 ST-BUS Outputs 2to 0 (5V-Tolerant Three-state Outputs). These are the pins for the eight 2048kbit/s ST-BUS output streams. ODE Output Drive Enable (5V-tolerant Input). If this input is held high, the STo0-STo7 output drivers function normally. If this input is low, the STo0-STo7 output drivers go into their high impedance state. NB: Even when ODE is high, channels on the STo0-STo7 outputs can go high impedance under software control. Control ST-BUS Output (5V-Tolerant Output). Each frame of 256 bits on this ST-BUS output contains the values of bit 1 in the 256 locations of the Connection Memory High. No Connection.
1
48
CSTo NC
6, 18, 6, 19, 28, 40 30, 43
2-5
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