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Details, datasheet, quote on part number:MT89L85
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| Part: | MT89L85 |
| Category: | Power Management => AC-DC Controllers/Converters => High & Low Side Switch |
| Description: | CMOS St-bus Family Enhanced Digital Switch |
| Company: | Mitel Networks Corporation |
| Datasheet: | Download MT89L85 datasheet File size : 137 kB |
| Request For quote: | Find where to buy MT89L85
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Datasheet text preview:
CMOS ST-BUSTM FAMILY MT89L85 Enhanced Digital Switch Advance Information
Features
· · · · · · · · · · · 3.3 volt supply 5V tolerant inputs and TTL compatible outputs 256 x 256 channel non-blocking switch Program m a bl e frame integrity for wideband channels Automati c identification of ST-BUS/GCI interface backplanes Per channel tristate control Patented message mode Non-mul t i p l exe d microprocessor interface Available in PLCC-44 and SSOP-48 packages Pin compatible with MT8985 device Low power consumption
DS5194 ISSUE 2 September 1999
O rd e r i n g Information M T 8 9 L 8 5 A P 4 4 Pin PLCC M T 8 9 L 8 5 A N 4 8 Pin SSOP -40°C to +85°C
Description
The MT89L85 Enhanced Digital Switch device is an upgraded 3-volt version of the MT8985 Digital Switch. It is pin compatible with the MT8985 and retains all of the MT8985's functionality. The enhanced digital swtich is designed for switching PCM-encoded voice or data, under microprocessor control, in digital exchanges, PBXs and any ST-BUS/ MVIP environment. It provides simultaneous connections for up to 256 64kb/s channels. Each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s stream. As the main function in switching applications, the device provides per-channel selection between variable or constant throughput delays. The constant throughput delay feature allows grouped channels such as ISDN H0 to be switched through the device maintaining its sequence integr ity. The MT89L85 is ideal for medium sized mixed voice/data switch and voice processing applications.
Applications
· · · · · · Medium size digital switch matrices Hypercha n n e l switching (e.g., ISDN H0) ST-BUS/ MV I P TM interface functions Ser ial bus control and monitoring Centralize d voice processing systems Data multiplexer
C4i
F0i RESET VDD VSS
**
ODE
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 Serial to Parallel Conver ter Data Memor y
Frame Counter
Output MUX Parallel to Serial Conver ter
STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7
Control Register Connection Memor y Control Interface
** for 48-pin SSOP only
DS CS R/W A5/ A0
DTA D7/ D0
CSTo
Fi gur e 1 - Functional Block Diagram
1
MT89L85
Advance Information
STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4
44 PIN PLCC
VSS DTA STi0 STi1 STi2 NC STi3 STi4 STi5 STi6 STi7 VDD RESET F0i C4i A0 A1 A2 NC A3 A4 A5 DS R/W
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
CSTo ODE STo0 STo1 STo2 NC STo3 STo4 STo5 STo6 STo7 VSS VDD D0 D1 D2 D3 D4 NC D5 D6 D7 CS VSS
NC A3 A4 A5 DS R/W CS D7 D6 D5 NC
18 19 20 21 22 23 24 25 26 27 28
6 5 4 3 2 1 44 43 42 41 40
NC STi2 STi1 STi0 DTA CSTo ODE STo0 STo1 STo2 NC
48 PIN SSOP (JEDEC MO-118, 300mil Wide)
Fi gure 2 - Pin Connections
Pin Description
Pin # 44 PLCC 2 3-5 7-11 12 48 SSOP 2 3-5 7-11 12,36 13 Name Description
DTA
Data Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is complete. A pull-up resistor is required at this output.
STi0- ST-BUS Input 0 to 7 (Inputs). Serial data input streams. These streams have 32 STi7 channels at data rates of 2.048 Mbit/s. VDD +3.3 Volt Power Supply. RESET Device Reset (5v-tolerant input). This pin is only available for the 48-pin SSOP package. This active low input puts the MT89L85 in its reset state. It clears the internal counters anf registers. All ST-BUS outputs are set to the high impedance state. This RESET pin must be held low for a minimum of 100nsec to reset the device. F0i Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to different backplane specifications such as ST-BUS and GCI. Clock (Input). 4.096 MHz serial clock for shifting data in and out of the data streams.
13
14
14 15-17 19-21 22
15 16-18 20-22 23
C4i
A0-A5 Address 0 to 5 (Inputs). These lines provide the address to MT89L85 internal registers. DS Data Strobe (Input). This is the input for the active high data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation.
2
Advance Information
Pin Description
Pin # 44 PLCC 23 24 25-27 29-33 34 35-39 41-43 44 48 SSOP 24 26 27-29 31-35 1,25,37 38-42 44-46 47 Name Description
MT89L85
R/W CS
Read/Write (Input). This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. Chip Select (Input). Active low input enabling a microprocessor read or write of control register or internal memories.
D7-D0 Data Bus 7 to 0 (Bidirectional). These pins provide microprocessor access to data in the internal control register, connect memory high, connect memory low and data memor y. VSS Ground Rail. STo7- ST-BUS Outputs 7 to 0 (Three-state Outputs). Serial data output streams. These STo0 streams are composed of 32 channels at data rates of 2.048 Mbit/s. ODE Output Drive Enable (Input). This is an output enable for the STo0 to STo7 serial outputs. If this input is low STo0-7 are high impedance. If this input is high each channel may still be put into high impedance by software control. CSTo Control ST-BUS Output (Output). This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CSTo bit in the Connect Memory high locations. NC No Connection. automatically identifies the polarity and format of frame synchronization input signals compatible to ST-BUS and GCI interfaces. Dev i c e Operation A functional block diagram of the MT89L85 device is shown in Figure 1. The serial ST-BUS streams operate continuously at 2.048 Mb/s and are arranged in 125 µs wide frames each containing 32 8-bit channels. Eight input (STi0-7) and eight output (STo0-7) serial streams are provided in the MT89L85 device allowing a complete 256 x 256 channel nonblocking switch matrix to be constructed. The serial interface clock for the device is 4.096 MHz, as required in ST-BUS and GCI specifications. Da t a Memory The received serial data is converted to parallel for mat by the on-chip serial to parallel converters and stored sequentially in a 256-position Data Memor y. The sequential addressing of the Data Memor y is generated by an internal counter that is reset by the input 8 kHz frame pulse (F0i) marking the frame boundaries of the incoming serial data streams. Depending on the type of information to be switched, the MT89L85 device can be programmed to perform
3
1
48
6,18, 28,40
6,19,30, 43
F u n ction a l Description
With the integration of voice, video and data services into the same network, there has been an increasing demand for systems which ensure that data at N x 64 Kbit/s rates maintain frame sequence integrity while being transported through time slot interchange circuits. Existing requirements demand time slot interchange devices performing switching with constant throughput delay while guaranteeing minimum delay for voice channels. The MT89L85 device provides both functions and allows existing systems based on the MT8985 to be easily upgraded to maintain the data integrity while multiple channel data are transported. The device is designed to switch 64 kbit/s PCM or N x 64 kbit/s data. The MT89L85 can provide both frame integrity for data applications and minimum throughput switching delay for voice applications on a per channel basis. By using Mitel Message mode capability, the microprocessor can access input and output time slots on a per channel basis to control devices such as the MITEL MT8972, ISDN Transceivers and T1/ CEPT trunk interfaces through the ST-BUS interface. Different digital backplanes can be accepted by the MT89L85 device without user's intervention. The MT89L85 device provides an internal circuit that
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