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Details, datasheet, quote on part number:MT89L86
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| Part: | MT89L86 |
| Category: | Power Management => AC-DC Controllers/Converters => High & Low Side Switch |
| Description: | CMOS St-bus Family Multiple Rate Digital Switch |
| Company: | Mitel Networks Corporation |
| Datasheet: | Download MT89L86 datasheet File size : 178 kB |
| Request For quote: | Find where to buy MT89L86
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Datasheet text preview:
CMOS ST-BUSTM FAMILY
MT89L86
Multiple Rate Digital Switch Advance Information
Features
· · · · · · · · · · · · · 3.3 volt supply 5V tolerant inputs and TTL compatible outputs. 256 x 256 or 512 x 256 switching configurations 8-bit or 4-bit channel switching capability Guarante e s frame integrity for wideband channels Automati c identification of ST-BUS/GCI interface s Accepts serial streams with data rates of 2.048, 4.096 or 8.192 Mb/s Rate conversion from 2.048 Mb/s to 4.096 or 8.192 Mb/s and vice-versa Program m a bl e frame offset on inputs Per-chan n e l three-state control Per-chan n e l message mode Control interface compatible to Intel/Motorola CPUs Low power consumption
DS5195 ISSUE 2 September 1999
O rd e r i n g Information MT89L86AP MT89L86AN 44 Pin PLCC 48 Pin SSOP
-40°C to +85°C
Description
The 3.3V Multiple Rate Digital Switch (MT89L86) is pin compatible with MITEL's 5V MT8986 and retains all of its functionality. This 3.3v device is designed to provide simultaneous non-blocking connections for up to 256 64kb/s channels or blocking connections for up to 512 64kb/s channels. The serial inputs and outputs may have 32 to 128 64kb/s channels per frame with data rates ranging from 2048 up to 8192 kb/s. It also provides per-channel selection between var iable and constant throughput delays allowing voice and grouped data channels to be switched without corrupting the data sequence integrity.
Applications
· · · · · · · Medium size mixed voice and data switching/ processi n g matrices Hypercha n n e l switching (e.g., ISDN H0) MVIP TM interface functions Ser ial bus control and monitoring Centralize d voice processing systems Voice/Da t a multiplexer ADPCM 32 kbit/s channel switching
** VDD RESET
VSS
ODE
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15
Serial to Parallel Conver ter Timing Unit
Multiple Buffer Data Memory
Output MUX Parallel to Serial Conver ter Connection Memor y
Internal Registers
Microprocessor Interface
STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 STo9
** for 48-pin SSOP only
CLK FR AS/ IM ALE
DS CS RD
R/W A0/ DTA AD7/ AD0 WR A7
CSTo
Fi g u r e 1 - Functional Block Diagram
1
MT89L86
Advance Information
AS/ALE STi2 STi1 STi0 DTA CSTo ODE STo0 STo1 STo2 STi14/STo8
STi3 STi4 STi5 STi6/A6 STi7/A7 VDD FR CLK STi8/A0 STi9/A1 STi10/A2
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 IM STi11/A3 STi12/A4 STi13/A5 DS/RD R/W/WR CS AD7 AD6 AD5 STi15/STo9
STo3 STo4 STo5 STo6/A6 STo7/A7 VSS AD0 AD1 AD2 AD3 AD4
VSS DTA STi0 STi1 STi2 AS/ALE STi3 STi4 STi5 STi6/A6 STi7/A7 VDD RESET FR CLK STi8/A0 STi9/A1 STi10/A2 IM STi11/A3 STi12/A4 STi13/A5 DS/RD R/W\WR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 PIN SSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
CSTo ODE STo0 STo1 STo2 STi14/STo8 STo3 STo4 STo5 STo6/A6 STo7/A7 VSS VDD AD0 AD1 AD2 AD3 AD4 STi15/STo9 AD5 AD6 AD7 CS VSS
44 PIN PLCC
(JEDEC MO-118, 300mil Wide)
Fi gure 2 - Pin Connections
Pin Description
Pin # 44 48 PLCC SSOP 2 3-5 7-9 10 2 3-5 7-9 10 Name Description
DTA STi0-5
Data Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. ST-BUS Inputs 0 to 5 (5V-tolerant Inputs). Serial data input streams. These streams may have data rates of 2.048, 4.096 or 8.192 Mbit/s with 32, 64 or 128 channels, respectively. ST-BUS Input 6/Addr.6 input (5V-tolerant Input). The function of this pin is determined by the switching configuration enabled. If non-multiplexed CPU bus is used along with a higher input rate of 8.192 or 4.096 Mb/s, this pin provides A6 address input function. For 2.048 and 4.096 Mb/s (8x4) applications or when the multiplexed CPU bus interface is selected, this pin assumes STi6 function. See Control Register bits description and Tables 1, 2, 6 & 7 for more details. Note that for applications where both A6 and STi6 inputs are required simultaneously (e.g., 8 x 4 switching configuration at 4.096 Mb/s or rate conversion between 2.048Mb/ s to 4.196 or 8.192 Mb/s) the A6 input should be connected to pin STo6/A6. ST-BUS Input 7/Addr.7 input (5V-tolerant Input): The function of this pin is determined by the switching configuration enabled. If non-multiplexed CPU bus is used along with a higher input rate of 8.192 Mb/s, this pin provides A7 address input function. For 2.048 and 4.096 Mb/s (8x4) applications or when the multiplexed CPU bus is selected, this pin assumes STi7 function. See Control Register bits description and Tables 1, 2, 6 & 7 for more details. Note that for applications where both A7 and STi7 inputs are required simultaneously (e.g., 2.048 to 8.192 Mb/s rate conversion) the A7 input should be connected to pin STo7/A7.
STi6/A6
11
11
STi7/A7
2
Advance Information
Pin Description (continued)
Pin # 44 48 PLCC SSOP 12 12,36 13 Name Description
MT89L86
VDD RESET
+3.3 Volt Power Supply. Device Reset ( 5v-tolerant input). This pin is only available for the 48-pin SSOP package. In normal operation, This active low input puts the MT89L86 in its reset state. It clears the internal counters and registers. All ST-BUS outputs are set to the high impedance state. The RESET pin must be held low for a minimum of 100nsec to reset the device. Frame Pulse (5V-tolerant Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS and GCI interface specifications. Clock (5V-tolerant Input). Serial clock for shifting data in/out on the serial streams. Depending on the serial interface speed selected by IMS (Interface Mode Select) register, the clock at this pin can be 4.096 or 8.192 MHz.
13
14
FR
14
15
CLK
15-17 16-18
STi8/A0, Address 0-2 / Input Streams 8-10 (5V-tolerant Input). When the non-multiplexed CPU STi9/A1, bus is selected, these lines provide the A0-A2 address lines to the MT89L86 internal STi10/A2 registers. When the 16x8 switching configuration is selected, these pins are ST-BUS serial inputs 8 to 10 receiving data at 2.048 Mb/s.
19-21 20-22 STi11/A3, Address 3-5 / Input Streams 11-13 (5V-tolerant Input). When the non-multiplexed STi12/A4, CPU bus is selected, these lines provide the A3-A5 address lines to the MT89L86 STi13/A5 internal registers. When the 16x8 switching configuration is selected, these pins are ST-BUS serial inputs 11 to 13 receiving data at 2.048 Mb/s. 22 23 DS/RD Data Strobe/Read (5V-tolerant Input). When the non-multiplexed CPU bus or Motorola multiplexed bus is selected, this input is DS. This active high input works in conjunction with CS to enable read and write operation. For the Intel/National multiplexed bus interface, this input is RD. This active low input configures the data bus lines (AD0-7) as outputs.
23
24
R/W\WR Read/Write \ Write (5V-tolerant Input). For the non-multiplexed or Motorola multiplexed bus interface, this input is R/W. This input controls the direction of the data bus lines (AD0-AD7) during a microprocessor access. For the Intel/National multiplexed bus interface, this input is WR. This active low signal configures the data bus lines (AD0-7) as inputs. CS Chip Select (5V-tolerant Input). This active low input enables a microprocessor read or write of the MT89L86's internal control register or memories.
24
26
25-27 27-29 AD7-AD0 Data Bus (Bidirectional): These pins provide microprocessor access to the internal 29-33 31-35 control registers, connection memories high and low and data memories. For the multiplexed bus interface these pins also provide the input address to the internal Address Latch circuit. 34 35 1, 25,37 38 VSS Ground.
STo7/A7 ST-BUS Output 7/Address 7 input (Three-state output/input). The function of this pin is determined by the switching configuration enabled. If non-multiplexed CPU bus is used along with data rates employing 8.192 Mb/s rates, this pin provides A7 address input function. For 2.048 Mb/s applications or when the multiplexed CPU bus interface is selected, this pin assumes STo7 function. See Tables 1, 2, 6 & 7 for more details. Note that for applications where A7 input and STo7 output are required simultaneously (e.g., 8.192 to 2.048 Mb/s rate conversion), the A7 input should be connected to pin STi7/A7.
3
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