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Details, datasheet, quote on part number:MT90810
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Datasheet text preview:
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CMOS MT90810 Flexible MVIP Interface Circuit Preliminary Information
Feature s
· · M V I P and ST-BUS compliant M V I P Enhanced Switching with 384x384 channel capacity (256 MVIP channels; 128 local channels) On - c hi p PLL for MVIP master/slave operation Lo c al output clocks of 2.048,4.096,8.192MHz with programmable polarity Lo c al serial interface is programmable to 2.048, 4.096, or 8.192Mb/s with associated clock outputs A dd it io na l control output stream P er - c h an n e l message mode Tw o independently programmable groups of up to 12 framing signals each M ot or o la non-multiplexed or Intel multiplexed/ n o n - m ul t ip le x e d microprocessor interface
TM TM
I SSUE 2
O ct ober 1994
O rd er i ng Information M T 9 0 81 0 A K 100 Pin PQFP
0 °C to +70 °C
· · ·
Des cr ip t io n
Mitel's MT90810 is a Flexible MVIP Interface Circuit (FMI C). The MVIP (Multi-Vendor Integration Protoc ol) compliant device provides a complete MVIP compliant interface between the MVIP Bus and a wide variety of processors, telephony interfaces and other circuits. A built-in digital time-slot switch provides MVIP enhanced switching between the full MVIP Bus and any combination of up to 128 full duplex local channels of 64kbps each. An 8 bit micropr ocessor port allows real-time control of switching and programming of device configuration. On-board clock circuitry, including both analog and digital phase-locked loops, supports all MVIP clock modes . The local interface supports PCM rates of 2. 048, 4.096 and 8.192Mb/s, as well as parallel DMA through the microprocessor port.
· · · · ·
Ap p l ic a t io n s
· · · · · M edi um size digital switch matrices M V I P interface functions S er i al bus control and monitoring C en t r al iz e d voice processing systems Voi c e/ D at a multiplexer
EX_8 KA
EX_8KB
X2
X1/CLKIN PLL_LO
PLL_LI
FRAM E
SE C8K
C4b C2o F0b DSo[0:7] DSi[0:7] LDO[0:3] LDI[0:3] TCK TMS TDI TDO
Timing and Clock Control (Oscillator and Analog & Digital PLLs) Enhanced Switch S -P/ P -S D ata Memory Connecti on Memory Program mable Fram ing Signals
CLK2 CLK4 CLK8 RESET
CSTo FGA[0:11] FGB[0:11]
JTAG
Microproces sor Interface
ERR
AD[0:7] A[0:1] ALE
WR / R/W
RD/ DS
CS
RDY/ DREQ[0:1] DACK[0:1] DTA CK
F ig u re 1 - Functional Block Diagram
2-145
MT90810
Preliminary Information
SEC8K VSS 52
FGB9 DSi6
FGA9
FGB8 DSi1
FGA8 C4b
LDO0 VSS
FGA10 LDO 1 LDO 2 FGB10 LDO 3 VDD LDI0 LDI1 LDI2 LDI3 EX8_KA EX8_KB VSS FR AME CLK8 FGA11 CLK4 CLK2 FGB11 FGA0
80 82
78
76
74
72
70
68
66
64
62
60
58
56
54
FGB7 50 48
DS o7
DS o6
DS o5
DSi4 DS o4
DS o3 VSS
DS o2
DS o1
DS o0
DSi7
DSi5
DSi3
DSi2
DSi0
VDD
C2o
F0b
DREQ1 DREQ0 DACK1 DACK0 FG A7 AD 7 AD 6 AD 5 AD 4 VSS VD D FG B6 AD 3 AD 2 AD 1 AD 0 A1 FG A6 A0 ER R
84 46 86 44 88 42 90 92 94 36 96 34 98 32 100 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 40 38
100 PIN PQFP
X1/CLKIN
RESET FGA5
VCO_VDD WR/[R/W]
VDD VSS
TCK TDI
PLL_LI
FGA1 FGA2
FGA3
CSTo
FGA4 FGB0
FGB1
FGB2
FGB3
FGB4
RD/[DS]
FGB5 ALE
Fi g u re 2 - Pin Connections
2-146
RDY/[DTACK]
X2
VC O_VSS
TMS
TDO
PLL_LO
CS
Preliminary Information
MT90810
Pin Description
Pin # 58, 60, 63, 67, 70, 72, 74, 77 59, 61, 64, 68, 71, 73, 75, 78 80, 82, 83, 85 87, 88, 89, 90 4 Name DSo[0:7] DSi[0:7] LDO[0:3] LDI[0:3] CSTo Description MVIP DSo Streams (Bidirectional CMOS). 2.048Mb/s serial data streams conforming to ST-BUS serial data stream specifications. MVIP DSi Streams (Bidirectional CMOS). 2.048Mb/s serial data streams conforming to ST-BUS serial data stream specifications. Local Output Serial Streams (Output). Serial data streams programmable to 2.048, 4.096 or 8.192Mb/s data rates. Local Input Serial Streams (TTL Input). Serial data streams programmable to 2.048, 4.096 or 8.192 Mb/s data rates. Control ST-BUS Output (Output). This is a 1.024Mb/s output. The state of each bit in this stream is determined by the CSTo bit in connection memory high. MVIP F0 signal (CMOS Input/Output). ST-BUS 8kHz framing signal MVIP C4 signal (CMOS Input/Output). ST-BUS 4.096MHz clock MVIP C2 signal (Output). ST-BUS 2.048MHz clock. This pin is automatically set to high impedance when it is not driven. MVIP SEC8K signal (CMOS Input/Output). A secondary 8kHz signal used either as an input source to the on-chip digital PLL or as an output to the MVIP bus. External 8kHz input A (TTL Input). External 8kHz input B (TTL Input). Local Frame Output Signal (Output). This 8kHz framing signal has a duty cycle and period equal to the MVIP F0 signal. 8MHz Local Output Clock (Output). This is a 8MHz clock. 4MHz Local Output Clock (Output). This 4MHz clock has a duty cycle and period equal to the MVIP C4 signal. 2MHz Local Output Clock (Output). This 2MHz clock has a duty cycle and period equal to the MVIP C2 signal. Frame Group A framing signals (Output). Programmable framing signals. The frame group outputs are determined by mode bits in the frame register to be either programmed outputs, output drive enables for DSo, or output framing pulses for use with local serial data streams. Frame Group B framing signals (Output). Programmable framing signals. The frame group outputs are determined by mode bits in the frame register to be either programmed outputs, output drive enables for DSi, or output framing pulses for use with local serial data streams. Chip Reset (Schmitt Input). This active low reset clears all internal registers, connection memory and data memory Microprocessor Address/Data Bus (Bidirectional TTL). Microprocessor access to internal registers, connection and data memories. In non-multiplexed mode: data bus. In multiplexed mode: multiplexed address and data bus.
55 56 54 53
F 0b C4b C2o SEC8K
91 92 94 95 97 98 100, 1, 2, 3, 5, 20, 33, 46, 57, 69, 81, 96
EX_8KA EX_8KB FRAME CLK 8 CLK 4 CLK 2 FGA[0:11]
6, 7, 8, 9, 14, 28, 39, 51, 62, 76, 84, 99 19 35, 36, 37, 38, 42, 43, 44, 45
FGB[0:11]
RESET AD[0:7]
2- 147
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