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Details, datasheet, quote on part number:MT90820
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| Part: | MT90820 |
| Category: | Power Management => AC-DC Controllers/Converters => High & Low Side Switch |
| Description: | CMOS St-bus Family Large Digital Switch ( LDX ) |
| Company: | Mitel Networks Corporation |
| Datasheet: | Download MT90820 datasheet File size : 71 kB |
| Request For quote: | Find where to buy MT90820
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Datasheet text preview:
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CMOS ST-BUSTM FAMILY MT90820 Large Digital Switch (LDX) Advance Information
Feature s
· · · · · · · · · · · · 2, 04 8 channel non-blocking switch M ai nt ai ns frame integrity on concatenated channels. P er - c h an n e l selection of minimum or constant throughput delay S er i al streams at 2.048, 4.096 or 8.192Mb/s Fr am e offset delay measurement P rog r am m ab le frame delay offset P e r - c h an n e l three-state control P er - c h an n e l message mode C on t r ol interface compatible to Intel/Motorola CPUs B lo c k programming feature for connection memory S T- B U S / M V I P and GCI interfaces Tes t Port compatible to IEEE-1149.1 standard
I SSUE 1
May 1995
O rd er i ng Information M T 90 82 0A P M T 9 0820A L 84 Pin PLCC 100 Pin QFP
-40 to +85°C
Des cr ip t io n
The Large Digital Switch (LDX) is an advanced digital switch allowing the users to build up to 2048 channel non-blocking switch. The serial interface can be at 2, 4 or 8 Mb/s compatible to ST-BUS/MVIP/ HM VIP or GCI standards. The LDX can be programmed to provide either minimum or constant throughput delay on all its channels. The device also feat ures three-state control and message mode on per -channel basis. To manage the problem of line delays, each input stream can have an individually programmed input frame offset delay. The offset delay can be calibrated with a dedicated frame measurement facility inside the device.
Ap p l ic a t io n s
· · · · · · M edi um and large switching platforms C . O . switches C T I application Voi c e/ d at a multiplexer D i git a l cross connects S T- B U S / H M V I P interface functions
VDD VSS TMS TDI TDO
TCK TRSTB TEST RESETB
ODE
Test Port STi 0 STi 1 STi 2 STi 3 STi 4 STi 5 STi 6 STi 7 STi 8 STi 9 STi 10 STi 11 STi 12 STi 13 STi 14 STi 15 Output M UX ST o0 ST o1 ST o2 ST o3 ST o4 ST o5 ST o6 ST o7 ST o8 ST o9 ST o1 0 ST o1 1 ST o1 2 ST o1 3 ST o1 4 ST o1 5
Se ria l to Pa ral lel Converte r
Multiple Buffer Data Memory
Parallel to Serial Converter
Internal Regi sters
Connection Mem ory
Timing Uni t
Microprocessor Interface
CLK FRM FE/ HMVIP HCLK
AS/ IM DS CS R/W ALE RD WR
A7-A0 D TA D15-D8/ CSTo AD7-AD0
Fi g ur e 1 - Functional Block Diagram
2-179
MT90820
CMOS
Advance Information
10
8
6
4
2
84
82
80
78
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 FRM FE/HCLK VSS CLK V DD
76
VSS ST015 STo14 STo13 ST012 STo11 STo10 STo9 STo8 V DD VSS STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 O DE VSS
12 14 16 18 20 22 24 26 28 30 46 48 34 36 38 40 42 44 50 32 52 74 72 70 68 66
84 PIN PLCC
64 62 60 58 56 54
CSTo DTA D15 D14 D13 D12 D11 D10 D9 D8 VS S VDD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VS S
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 FRM FE/HCL K VS S CLK
80 82
NC NC NC NC VSS ST015 STo14 STo13 ST012 STo11 STo10 STo9 STo8 VDD VSS STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 ODE VSS CSTo NC NC NC NC
78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 84 46 86 44 88 42 90 92 94 36 96 34 98 32 100 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 40 38
TMS T DI T DO T CK TRSTB TEST RESETB HMVIP A0 A1 A2 A3 A4 A5 A6 A7 DS/RD R/W\RW CS AS/ALE IM
100 PIN PQFP
DTA D1 5 D1 4 D1 3 D1 2 D11 D1 0 D9 D8 VSS V DD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VSS
2-1 80
NC NC NC NC VDD TMS TDI T DO T CK TRSTB TEST RESETB HMVIP A0 A1 A2 A3 A4 A5 A6 A7 DS/RD R/W\ RW CS AS/ALE IM NC NC NC NC
Fi g u re 2 - Pin Connections
Advance Information
Pin Description
Pin # 84 1, 11, 30, 54 64, 75 1 00 31, 41, 56, 66, 76, 99 5, 40, 67 6 8 - 75 81-96 97 Nam e VSS Ground. D e scri pti on
CMOS
MT90820
2, 32, 63 3 - 10 12 27 28
VDD STo8 - 15 STi0 - 15 FRM
+5 Volt Power Supply. Data Stream Output 8 to 15: Serial data Output stream. These stream may have data rates of 2.048, 4.096 or 8.192 Mb/s. Data Stream Input 0 to 15: Serial data input stream. These stream may have data rates of 2.048, 4.096 or 8.192. Frame Pulse (input): This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS and GCI interface specifications, when HMVIP pin =0. When HMVIP pin =1, FRM input accepts a negative frame pulse which conforms to HMVIP formats. Frame Measurement input, when HMVIP pin = 0. 4.096MHz Clock input, when HMVIP pin = 1. Clock (input): Serial clock for shifting data in/out on the serial stream. When 1, enable test mode for production testing. Test Data Input. Test Data Output. Test Clock input. Test Reset Input: When 0, resets the test circuit. Internal Connection: keep at 0 for normal operation. Device Reset Input: When 0, resets the device. HMVIP mode input. When 1, enables HMVIP interface. When 0, the device operates in ST-BUS/GCI mode. Address 0 - 7(Input): When non-multiplexed CPU bus is selected, these lines provide the A0 - A7 address lines to internal memories. Data Strobe/Read (input): When non-multiplexed CPU bus or Motorola multiplexed bus are selected, this input is DS. This active high input works in conjunction with CSB to enable read and write operation. For Intel multiplexed bus, this input is RDB. This active low input sets the data bus lines (AD0-AD7, D8-D15) as outputs. Read/Write \ Write (Input): In case of non-multiplexed and Motorola multiplexed buses, this input is Read/Write. This input controls the direction of the data bus lines (AD0 - AD7, D8-D15) during a microprocessor access. Chip Select (Input): Active low input enabling a microprocessor access of the device.
29 31 33 34 35 36 37 38 39 40 41 48 49
98 100 6 7 8 9 10 11 12 13 14-21 22
FE/HCLK CL K TMS T DI TDO T CK TRS TB IC RESETB HMVIP A0 - A7 DS /RD
50
23
R/W \W R
51
24
CS
2- 181
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