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Details, datasheet, quote on part number:MT90823
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| Part: | MT90823 |
| Category: | Power Management => AC-DC Controllers/Converters => High & Low Side Switch |
| Description: | 3v Large Digital Switch |
| Company: | Mitel Networks Corporation |
| Datasheet: | Download MT90823 datasheet File size : 154 kB |
| Request For quote: | Find where to buy MT90823
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Datasheet text preview:
MT90823
3V Large Digital Switch
Features
· · · · · · · · · · · · 2,048 × 2,048 channel non-blocking switching at 8.192 Mb/s Per-chann e l variable or constant throughput delay Automatic identification of ST-BUS/GCI interfaces Accept ST-BUS streams of 2.048, 4.096 or 8.192 Mb/s Automatic frame offset delay measurement Per-stream frame delay offset programming Per-chann e l high impedance output control Per-chann e l message mode Control interface compatible to Motorola non-multip l exe d CPUs Connection memory block programming 3.3V local I/O with 5V tolerant inputs and TTL-comp a t i bl e outputs IEEE-1149 . 1 (JTAG) Test Port
DS5064 ISSUE 3 January 2000
O rd e r i n g Information MT90823AP 84 Pin PLCC MT90823AL 100 Pin MQFP MT90823AB 100 Pin LQFP MT90823AG 120 Pin PBGA -40 to +85°C
Description
The MT90823 Large Digital Switch has a non-blocking switch capacity of: 2,048 x 2,048 channels at a serial bit rate of 8.192 Mb/s; 1,024 x 1,024 channels at 4.096 Mb/s; and 512 x 512 channels at 2.048 Mb/s. The device has many features that are programmable on a per stream or per channel basis, including message mode, input offset delay and high impedance output control. Per stream input delay control is particularly useful for managing large multi-chip switches that transport both voice channel and concatenated data channels. In addition, the input stream can be individually calibrated for input frame offset using a dedicated pin.
Applications
· · · · · · Medium and large switching platforms CTI application Voice/data multiplexer Digital cross connects ST-BUS/G C I interface functions Suppor t IEEE 802.9a standard
VDD VSS TMS TDI TDO TCK
TRST
IC
RESET
ODE
Test Port STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 STo9 STo10 STo11 STo12 STo13 STo14 STo15
Serial to Parallel Converter
Loopback Parallel Multiple Buffer Data Memory Output MUX to Serial Converter Internal Registers Connection Memory
Timing Unit
Microprocessor Interface
CLK
F0i
FE/ WFPS HCLK
AS/ IM DS/ CS R/W ALE RD /WR
A7-A0 DTA D15-D8/ CSTo AD7-AD0
Figure 1 - Functional Block Diagram
1
MT90823
CMOS
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 F0i FE/HCLK VSS CLK VDD
VSS STo15 STo14 STo13 STo12 STo11 STo10 STo9 STo8 VDD VSS STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 ODE VSS
10 13 15 17 19 21 23 25 27 29 31 34 36 38 40 42 44 46 48 50 8 6 4 2 84 82 80 78 76 73 71 69 67
84 PIN PLCC
65 63 61 59 57 55 52
CSTo DTA D15 D14 D13 D12 D11 D10 D9 D8 VSS VDD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VSS
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 F0i FE/HCLK VSS CLK
80 82
NC NC NC NC VSS STo15 STo14 STo13 STo12 STo11 STo10 STo9 STo8 VDD VSS STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 ODE VSS CSTo NC NC NC NC
78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 84 46 86 44 88 90 92 94 36 96 34 98 99 2 4 6 8 10 12 14 16 18 20 22 24 26 28 32 30 42 40 38
TMS TDI TDO TCK TRST IC RESET WFPS A0 A1 A2 A3 A4 A5 A6 A7 DS/RD R/W/RW CS AS/ALE IM
100 PIN MQFP (14mm x 20mm x 2.75mm)
DTA D15 D14 D13 D12 D11 D10 D9 D8 VSS VDD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VSS
2
NC NC NC NC VDD TMS TDI TDO TCK TRST IC RESET WFPS A0 A1 A2 A3 A4 A5 A6 A7 DS/RD R/W/RW CS AS/ALE IM NC NC NC NC
Fi gure 2 - PLCC and MQFP Pin Connections
CMOS
1 A B C D E STi4 F STi6 G STi8 H STi10 STi11 VDD J STi12 STi13 VSS K STi14 STi15 VDD L V F0i FE/HCLK SS M VSS N CLK TMS TDO TRST RESETA0 A2 A3 A5 A7 DS/RD CS IM VSS TDI TCK IC WFPS A1 A4 A6 A R/W/RW S/ALE SS V VSS VDD VSS VDD VSS VDD VSS VDD VSS AD0 AD1 VDD AD2 AD3 VSS AD4 AD5 STi9 VSS STi7 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13
MT90823
VSS VSS STi0 STi2
VSS VSS
STo14 STo12STo10 STo9 STo7 STo5 STo4 STo2 STo0 VSS STo15 STo13STo11 STo8 VSS VDD VSS VDD VSS STo6 STo3 STo1 ODE VSS VDD VSS VDD VSS DTA VDD D14 VSS D12
VSS VSS CSTo D15 D13 D11 D9 AD7
STi1 VSS STi3 VDD STi5 VSS
TOP VIEW
VDD D10
PBGA (23mm x 23mm x 2.13mm) (Ball Pitch = 1.5mm)
VSS D8 VDD AD6
1
- A1 corner is identified by metallized markings.
NC NC STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 F0i FE/HCLK VSS CLK VDD NC NC
76 78 80 82 84 86 88 90 92 94 96 98 100 2 4 6 8 10 12 14 16 18 20 22 24
NC NC VSS STo15 STo14 STo13 STo12 STo11 STo10 STo9 STo8 VDD VSS STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 ODE VSS NC NC
74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42
100 PIN LQFP (14mm x 14mm x 1.4mm) (Pin Pitch = 0.50mm)
40 38 36 34 32 30 28 26
NC NC CSTo DTA D15 D14 D13 D12 D11 D10 D9 D8 VSS VDD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VSS NC NC
Fi gur e 3 - PBGA and LQFP Pin Connections
NC NC TMS TDI TDO TCK TRST IC RESET WFPS A0 A1 A2 A3 A4 A5 A6 A7 DS/RD R/W/RW CS AS/ALE IM NC NC
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