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Details, datasheet, quote on part number:MT91L61
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| Part: | MT91L61 |
| Category: | Communication => ISDN => Codec/Audio Interface |
| Description: | ISO2-cmos 3 Volt Multi-featured Codec ( MFC ) |
| Company: | Mitel Networks Corporation |
| Datasheet: | Download MT91L61 datasheet File size : 150 kB |
| Request For quote: | Find where to buy MT91L61
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Datasheet text preview:
ISO2-CMOS MT91L60/61 3 Volt Multi-Featured Codec (MFC) Advance Information
Features
· · Single 2.7-3.6 volt supply operation MT91L61 version features a delayed framing pulse in SSI and ST-BUS modes to facilitate cascaded devices Program m a bl e µ-L aw / A -L aw Codec and Filters Program m a bl e ITU-T (G.711)/sign-magnitude coding Program m a bl e transmit, receive and side-tone gains Fully differential interface to handset transduc e rs - including 300 ohm receiver driver Flexible digital interface including ST-BUS/SSI Ser ial microport Low power operation ITU-T G.714 compliant Multiple power down modes
DS5224 ISSUE 3 August 1999
O rd e r i n g Information MT91L61AE MT91L60AE MT91L61AS MT91L60AS MT91L61AN MT91L60AN 24 Pin Plastic DIP (600 mil) 24 Pin Plastic DIP (600 mil) 2 4 Pin SOIC 2 0 Pin SOIC 24 Pin SSOP 2 0 Pin SSOP -40°C to +85°C
· · · · · · · · ·
Description
The MT91L60/61 3V Multi-featured Codec incor porates a built-in Filter/Codec, gain control and programmable sidetone path as well as on-chip anti-alias filters, reference voltage and bias source. The device supports both ITU-T and sign- magnitude A-Law and µ-Law requirements. The MT91L60/61 is a true 3V device employing a fully differential architecture to ensure wide dynamic range. Complete telephony interfaces are provided for connection to handset transducers. Internal register access is provided through a serial microport compatible with various industry standard micro-controllers. The MT91L60/61 is fabricated in Mitel's ISO2-CMOS technology ensuring low power consumption and high reliability.
Applications
· · · · · · Batter y operated equipment Digital telephone sets Cellular radio sets Local area communications stations Pair Gain Systems Line cards
VSSD VDD VSSA VBias VRef
FILTER/CODEC GAIN MENCODER DECODER 7dB -7dB Transducer Interface M+
HSPKR + HSPKR -
Din Dout STB/F0i CLOCKin STBd/FOod (MT91L61only) Flexible Digital Interface
Timing
ST-BUS C&D Channels Serial Microport A/µ/IRQ
PWRST
IC
CS
DATA1
DATA2
SCLK
Fi g u r e 1 - Functional Block Diagram
1
MT91L60/61
MT91L60AS/AN
VBias VRef NC PWRST IC A/µ/IRQ VSSD CS NC SCLK DATA1 DATA2
Advance Information
MT91L60AE
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 M+ MVSSA NC HSPKR + HSPKR VDD CLOCKin NC STB/F0i Din Dout
MT91L61AE/AS/AN
VBias VRef NC PWRST IC A/µ/IRQ VSSD CS NC SCLK DATA1 DATA2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 M+ MVSSA NC HSPKR + HSPKR VDD CLOCKin STBd/FOod STB/F0i Din Dout
VBias VRef PWRST IC A/µ/IRQ VSSD CS SCLK DATA1 DATA2
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
M+ MVSSA HSPKR + HSPKR VDD CLOCKin STB/F0i Din Dout
20 PIN SOIC/SSOP
24 PIN PDIP
24 PIN PDIP/SOIC/SSOP
Fi gur e 2 - Pin Connections
Pin Description
Pin # 20 Pin 24 Pin 1 2 3 4 5 1 2 4 5 6 Name VBias VRef Description Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers. Connect 0.1 µF capacitor to VSSA. Reference Voltage for Codec (Output). Used internally. Nominally [Vdd/2 - 1.1] volts. Connect 0.1 µF capacitor to VSSA.
PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low). IC Internal Connection. Tie externally to VSSD for normal operation. A/µ/IRQ A/µ - When internal control bit DEn = 0 this CMOS level compatible input pin governs the companding law used by the filter/Codec; µ-Law when tied to VSSD and A-Law when tied to VDD. Logically OR'ed with A/µ register bit. IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt output signalling valid access to the D-Channel registers in ST-BUS mode. VSSD CS SCLK Digital Ground. Nominally 0 volts. Chip Select (Input). This input signal is used to select the device for microport data transfers. Active low. CMOS level compatible. Serial Port Synchronous Clock (Input). Data clock for microport. CMOS level compatible.
6 7 8 9
7 8 10 11
DATA 1 Bidirectional Serial Data. Por t for microprocessor serial data transfer. In Motorola/ National mode of operation, this pin becomes the data transmit pin only and data receive is performed on the DATA 2 pin. Input CMOS level compatible. DATA 2 Serial Data Receive. In Motorola/National mode of operation, this pin is used for data receive. In Intel mode, serial data transmit and receive are performed on the DATA 1 pin and DATA 2 is disconnected. Input CMOS level compatible. Dout Data Output. A high impedance three-state digital output for 8 bit wide channel data being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent with the rising edge of the bit clock during the timeslot defined by STB, or according to standard ST-BUS timing. Data Input. A digital input for 8 bit wide channel data received from the Layer 1 transceiver. Data is sampled on the falling edge of the bit clock during the timeslot defined by STB, or according to standard ST-BUS timing. Input level is CMOS compatible.
10
12
11
13
12
14
Din
2
Advance Information
Pin Description (continued)
Pin # 20 Pin 24 Pin 13 15 Name Description
MT91L60/61
STB/F0i Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit timeslot used by the device for both transmit and receive data. This active high signal has a repetition rate of 8 kHz. Standard frame pulse definitions apply in ST-BUS mode. CMOS level compatible input. Delayed Frame Pulse Output. In SSI mode, an 8 bit wide strobe is output after the first strobe goes low. In ST-BUS mode, a frame pulse is output after 4 channel (MT91L61 timeslots.
only)
16
STBd/ F0od
14
17
CLOCKin Clock (Input). The clock provided to this input pin is used for the internal device functions. For SSI mode connect the bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this input when the available bit clock is 128 kHz or 256 kHz. For ST-BUS mode connect C4i to this pin. CMOS level compatible. VDD Positive Power Supply (Input). Nominally 3 volts.
15 16 17 18 19 20
18 19 20 22 23 24 3,9, 16,21
HSPKR- Inverting Handset Speaker (Output). Output to the handset speaker (balanced). HSPKR+ Non-Inverting Handset Speaker (Output). Output to the handset speaker (balanced). VSSA MM+ NC Analog Ground (Input). Nominally 0 volts. Inverting Microphone (Input). Inverting input to microphone amplifier from the handset microphone. Non-Inverting Microphone (Input). Non-inver ting input to microphone amplifier from the handset microphone. No Connect. (24 Packages only). Pin 16 is NC for MT91L60.
O v e r v i ew
The 3V Multi-featured Codec (MFC) features complete Analog/Digital and Digital/Analog conversion of audio signals (Filter/Codec) and an analog interface to a standard handset transmitter and receiver (Transducer Interface). The receiver amplifier is capable of driving a 300 ohm load. Each of the programmable parameters within the functional blocks is accessed through a serial microcontroller port compatible with Intel MCS-51®, Motorola SPI® and National Semiconductor Microwire® specifications. These parameters include: gain control, power down, mute, B-Channel select (ST-BUS mode), C&D channel control/access, law control, digital interface programming and loopback. Optionally the device may be used in a controller less mode utilizing the power-on default settings.
F u n ct i o n al Description
Filter/Codec The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are programmable. These are ITU-T G.711 A-law or µ-Law, with true-sign/Alternate Digit Inversion or true-sign/Inverted Magnitude coding, respectively. Optionally, sign-magnitude coding may also be selected for proprietary applications. The Filter/Codec block also implements transmit and receive audio path gains in the analog domain. A programmable gain, voice side-tone path is also included to provide proportional transmit speech feedback to the handset receiver. This side tone path feature is disabled by default. Figure 3 depicts the nominal half-channel and side-tone gains for the MT91L60/61.
3
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